3.3.22. Four Activate Window Timing Register

The t_faw Register characteristics are:


Controls the four bank activate time in memory clock cycles, see Figure 2.16.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.29 shows the t_faw Register bit assignments.

Figure 3.29. t_faw Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.23 shows the t_faw Register bit assignments.

Table 3.23. t_faw Register bit assignments

[31:13]-Read undefined, write as zero.
[12:8]schedule_fawt_faw in aclk clock cycles, minus 3. Used as a scheduler delay. Supported values are 0-31.
[7:5]-Read undefined, write as zero.
[4:0]t_fawSets tFAW, the four-bank activate period in memory clock cycles. Supported values are 1-31.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E