3.3.9. ACTIVE to PRECHARGE Timing Register

The t_ras Register characteristics are:

Purpose

Controls the ACTIVE to PRECHARGE delay in memory clock cycles, see Figure 2.20.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.16 shows the t_ras Register bit assignments.

Figure 3.16. t_ras Register bit assignments

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Table 3.10 shows the t_ras Register bit assignments.

Table 3.10. t_ras Register bit assignments

BitsNameFunction
[31:5]-Read undefined, write as zero.
[4:0]t_rasSets tRAS, the ACTIVE to PRECHARGE delay in memory clock cycles. Supported values are 1-31.

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