3.3.8. MODEREG to Command Timing Register

The t_mrd Register characteristics are:


Controls the MODEREG to command delay in memory clock cycles, see Figure 2.21.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.15 shows the t_mrd Register bit assignments.

Figure 3.15. t_mrd Register bit assignments

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Table 3.9 shows the t_mrd Register bit assignments.

Table 3.9. t_mrd Register bit assignments

[31:7]-Read undefined, write as zero
[6:0]t_mrdSets tMRD, the time delay, in mclk cycles, for the DDR2 DMC to issue a command after it issues a MODEREG command. Supported values are 1-127.

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