3.3.31. Feature Control Register

The feature_ctrl Register characteristics are:

Purpose

Controls the:

  • early write response behavior

  • write burst behavior.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.38 shows the feature_ctrl Register bit assignments.

Figure 3.38. feature_ctrl Register bit assignments

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Table 3.32 shows the feature_ctrl Register bit assignments.

Table 3.32. feature_ctrl Registers bit assignments

BitsNameFunction
[31:3]-Read undefined, write as zero
[2]stop_wr_blocking

Controls the write merge up to memory burst:

0 = write transfers initiated when a full write memory burst is ready

1 = write transfers initiated when write data is available

[1]-Read undefined, write as zero
[0]stop_early_bresp

Controls the early write response feature:

0 = early write response enabled

1 = early write response disabled


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