3.3.1. Memory Controller Status Register

The memc_status Register characteristics are:


Provides information about the configuration and current state of the DDR2 DMC.

Usage constraints

Not accessible in the Reset or Power On Reset (POR) state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.8 shows the memc_status Register bit assignments.

Figure 3.8. memc_status Register bit assignments

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Table 3.2 shows the memc_status Register bit assignments.

Table 3.2. memc_status Register bit assignments

[31:14]-Read undefined.



Returns the maximum number of banks per memory chip:

0b00 = 4 banks

0b01 = 2 banks, not supported

0b10 = 1 banks, not supported

0b11 = 8 banks.

This field is configured by the Memory Banks per Chip [a] option.



Returns the number of exclusive access monitor resources implemented in the controller:

0b00 = 0 monitors

0b01 = 1 monitor

0b10 = 2 monitors

0b11 = 4 monitors.

This field is configured by the Exclusive Monitors [a] option.

[9]-Undefined, read as zero.



Returns the number of different chip selects that a configured controller supports:

0b00 = 1 chip

0b01 = 2 chips

0b10 = 3 chips

0b11 = 4 chips.

This field is configured by the Memory Chips [a] option.



Returns the type of SDRAM that the controller supports:

0b000-0b100 = reserved

0b101 = DDR2 SDRAM

0b110- 0b111 = reserved.



Returns the memory data bus width, MEMWIDTH, between the PHY and DDR2 SDRAM:

0b00 = 16-bit

0b01 = 32-bit

0b10 = 64-bit

0b11 = reserved.

This field is configured by the Memory Bus Width [a] option.



Returns the state of the memory controller:

0b00 = Config

0b01 = Ready

0b10 = Paused

0b11 = Low_power.


In DFI implementations the status of the controller must match that of the memory when tctrl_delay > 1. When software reads this field, it must wait tctrl_delay cycles before it can execute any action in the new state. For example, if entering Low_power to adjust the memory clock frequency, first the command is sent to the PHY before the controller updates its state. The system must wait tctrl_delay cycles before the self-refresh propagates to alter the clock.

[a] See the CoreLink DDR2 Dynamic Memory Controller (DMC-341) Supplement to AMBA Designer (ADR-301) User Guide for information about configuring this option.

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