3.3.5. Refresh Period Register

The refresh_prd Register characteristics are:

Purpose

Controls the memory refresh period in memory clock cycles.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.12 shows the refresh_prd Register bit assignments.

Figure 3.12. refresh_prd Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.6 shows the refresh_prd Register bit assignments.

Table 3.6. refresh_prd Register bit assignments

BitsNameFunction
[31:15]-Read undefined, write as zero
[14:0]refresh_prdMemory refresh period in memory clock cycles. Supported values are 63-32767.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910