CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference ManualRevision: r1p1
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3.3.5. Refresh Period Register

The refresh_prd Register characteristics are:

Purpose

Controls the memory refresh period in memory clock cycles.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.12 shows the refresh_prd Register bit assignments.

Figure 3.12. refresh_prd Register bit assignments

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Table 3.6 shows the refresh_prd Register bit assignments.

Table 3.6. refresh_prd Register bit assignments

BitsNameFunction
[31:15]-Read undefined, write as zero
[14:0]refresh_prdMemory refresh period in memory clock cycles. Supported values are 63-32767.

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