3.3.21. Memory Configuration 3 Register

The memory_cfg3 Register characteristics are:


Controls the refresh timeout setting.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.28 shows the memory_cfg3 Register bit assignments.

Figure 3.28. memory_cfg3 Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.22 shows the memory_cfg3 Register bit assignments.

Table 3.22. memory_cfg3 Register bit assignments

[31:3]-Read undefined, write as zero.
[2:0]refresh_timeoutSets the number of acceptable outstanding refreshes for a memory device, before the DDR2 DMC generates a refresh timeout. If this occurs, the arbiter entry moves to the highest priority in the queue, see Arbitration algorithm. Supported values are 1-7.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E