3.3.26. QoS Configuration Registers

The id_<n>_cfg Register characteristics are:


Sets the parameters for QoS <n>. Where <n> is a value from 0 to 15 and is the result of applying the 4-bit QoS mask to the arid[ ] bus.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.33 shows the id_<n>_cfg Register bit assignments.

Figure 3.33. id_<n>_cfg Registers bit assignments

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Table 3.27 shows the id_<n>_cfg Register bit assignments.

Table 3.27. id_<n>_cfg Registers bit assignments

[31:10]-Read undefined, write as zero.
[9:2]qos_max<n>Sets the maximum QoS value. Supported values are 0-255.

Enables the minimum QoS functionality:

0 = disabled, so the arbiter entry uses the qos_max<n> value

1 = enabled. the arbiter entry uses minimum latency.

[0]qos_enable<n>When set, the DDR2 DMC can apply QoS to a read transfer if the masking of the arid[ ] bits with the programmed QoS mask produces a value of <n>. See Quality of Service for more information.

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