3.3.12. AUTO REFRESH to Command Timing Register

The t_rfc Register characteristics are:

Purpose

Controls the AUTO REFRESH to command delay in memory clock cycles, see Figure 2.19.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.19 shows the t_rfc Register bit assignments.

Figure 3.19. t_rfc Register bit assignments

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Table 3.13 shows the t_rfc Register bit assignments.

Table 3.13. t_rfc Register bit assignments

BitsNameFunction
[31:16]-Read undefined, write as zero.
[15:8]schedule_rfcSets the AUTO REFRESH to command delay in aclk clock cycles minus 3. It is used as a scheduler delay and values in the range 0-255 are supported.
[7:0]t_rfcSets tRFC, the AUTO REFRESH to command delay in memory clock cycles. Supported values are 1-255.

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