3.3.19. Self-refresh to Command Timing Register

The t_esr Register characteristics are:

Purpose

Controls the self-refresh to command delay in memory clock cycles, see Figure 2.22.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.26 shows the t_esr Register bit assignments.

Figure 3.26. t_esr Register bit assignments

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Table 3.20 shows the t_esr Register bit assignments.

Table 3.20. t_esr Register bit assignments

BitsNameFunction
[31:8]-Read undefined, write as zero.
[7:0]t_esrSets the self-refresh to command delay in memory clock cycles. Supported values are 1-255.

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