CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 3.3.20. Memory Configuration 2 Register

3.3.20. Memory Configuration 2 Register

The memory_cfg2 Register characteristics are:

Purpose

Controls the operation of the DDR2 DMC. Enables you to override the configuration set by the tie-off signals, see Tie-offs.

Usage constraints

Only accessible in Config or Low_power state.
Some bits are only available when a controller is configured to provide a legacy pad interface.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.27 shows the memory_cfg2 Register bit assignments.

Figure 3.27. memory_cfg2 Register bit assignments

Table 3.21 shows the memory_cfg2 Register bit assignments.

Table 3.21. memory_cfg2 Register bit assignments

Bits	Name	Function
[31:8]	-	Read undefined, write as zero.
[7:6]	memory_width2	Controls if the DDR2 DMC uses the entire configured memory data bus width or half of the data bus. Depending on the configured MEMWIDTH value, the following bit settings are possible: `0b00` = memory device uses a 16-bit data bus. You can select this setting when MEMWIDTH=16 or MEMWIDTH=32. The controller uses the entire data bus when MEMWIDTH=16 and half of the data bus when MEMWIDTH=32. Note Do not use this setting if the controller uses an AXI data width of 128bits. See Supported memory widths. `0b01` = memory device uses a 32-bit data bus.You can select this setting when MEMWIDTH=32 or MEMWIDTH=64. The controller uses the entire data bus when MEMWIDTH=32 and half of the data bus when MEMWIDTH=64. `0b10` = memory device uses a 64-bit data bus.You can select this setting when MEMWIDTH=64. The controller uses the entire data bus. `0b11` = reserved. You can determine the configured data bus width, MEMWIDTH, by accessing the memory_width field in the memc_status Register, see Memory Controller Status Register. The default value is set by the state of memory_width[1:0], when aresetn goes HIGH.
[5:4]	bank_bits	Controls how many bits of the AXI address are allocated for addressing the banks in a memory device. The options are: `0b00` = 2 bits. Use this when a memory device contains a maximum of 4 banks. `0b01` = reserved. `0b10` = reserved. `0b11` = 3 bits. Use this when a memory device contains 8 banks and the controller configuration supports 8 banks. You can determine the configured number of supported memory banks by accessing the memory_banks field in the memc_status Register, see Memory Controller Status Register. The default value is set by the state of bank_bits[1:0], when aresetn goes HIGH.
[3]	cke_init	If the DDR2 DMC contains a DFI pad interface then this bit is reserved. Otherwise, for a controller with a legacy pad interface, it sets the state of cke when mresetn is deasserted. The default value is set by the state of cke_init, when aresetn goes HIGH.
[2]	dqm_init	If the DDR2 DMC contains a DFI pad interface then this bit is reserved. Otherwise, for a controller with a legacy pad interface, it sets the state of the dqm[MEMORY_BYTES-1:0] outputs when mresetn is deasserted. The default value is set by the state of dqm_init, when aresetn goes HIGH.
[1:0]	clock_cfg	Encodes the clocking scheme: `0b00` = aclk and mclk are asynchronous `0b01` = aclk and mclk are synchronous `0b10` - `0b11` = reserved. The default value of bit [0] is set by the state of sync, when aresetn goes HIGH.

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3.3.20. Memory Configuration 2 Register

Note