3.3.4. Memory Configuration Register

The memory_cfg Register characteristics are:


Controls the operation of the DDR2 DMC.

Usage constraints

Only accessible in Config or Low_power state.


Available in all configurations of the DDR2 DMC.


See the register summary in Table 3.1.

Figure 3.11 shows the memory_cfg Register bit assignments.

Figure 3.11. memory_cfg Register bit assignments

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Table 3.5 shows the memory_cfg Register bit assignments.

Table 3.5. memory_cfg Register bit assignments

[31:23]-Read undefined, write as zero.



Enables the DDR2 DMC to generate refresh commands for the following number of memory chips:

0b00 = 1 chip

0b01 = 2 chips

0b10 = 3 chips

0b11 = 4 chips.

It is only possible to generate commands up to and including the number of chips in the configuration that the memc_status Register defines, see Memory Controller Status Register.



Controls which bits of the arid bus that the controller uses when it selects the QoS value for an AXI read transfer:

0b000 = arid[3:0]

0b001 = arid[4:1]

0b010 = arid[5:2]

0b011 = arid[6:3]

0b100 = arid[7:4]

0b101 = arid[8:5]

0b110 = arid[9:6]

0b111 = arid[10:7].

See Quality of Service for more information.



Controls how many data accesses that the controller performs to a memory device, for each Read or Write command:

0b010 = burst of 4

0b011 = burst of 8

others = reserved.

The chosen burst value must also be programmed into the mode register of the DDR2 SDRAM using the direct_cmd Register. See Direct Command Register.


This enables the controller to stop the clock to the SDRAMs after the memory devices enter self-refresh mode.

When set to 1, if the DDR2 DMC implements a:

Legacy pad interface

It dynamically stops the clk_out[MEMORY_CHIPS-1:0] signals.

DFI pad interface

It sets dfi_dram_clk_disable[MEMORY_CHIPS-1:0] HIGH.

[13]auto_power_downWhen this is set, the memory interface automatically places the DDR2 SDRAMs into power-down state by deasserting cke, or dfi_cke, when the command FIFO has been empty for power_dwn_prd memory clock cycles.



Number of memory clock cycles for auto power-down of the DDR2 SDRAMs.

You must only change this field when either:

  • auto_power_down bit is 0

  • DDR2 DMC is in the Low_power state.

[6]-Reserved. Ignored for writes, read as zero.



Encodes the number of bits of the AXI address that comprise the row address:

0b000 = reserved

0b001 = reserved

0b010 = 13 bits

0b011 = 14 bits

0b100 = 15 bits

0b101 = 16 bits

0b110 - 0b111 = reserved.



Encodes the number of bits of the AXI address that comprise the column address:

0b000 = reserved.

0b001 = 9 bits.

0b010 = 10 bits.

0b011 = 11 bits. This means that A0-A9, and A11 are used for column address because A10 is a dedicated AP bit.

0b100 - 0b111 = reserved.

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