2.2.11. Pad interface

You can configure the DDR2 DMC can be configured to contain one of the following pad interfaces:

Legacy pad interface

The legacy pad interface is a replaceable block designed to operate with DDR2 SDRAM memory. It provides a register for each external signal.

You can replace or modify the legacy pad interface, if required, for additional optimization for a particular memory type or target library, or to use a hard macro.

If the legacy pad interface is modified or replaced, it is important that the relative timings of the control output signals enabled by command_en and data_cntl_en signals are maintained to ensure the timings carried out in the memory interface block are still correct at the external memory bus interface. The read_en signal is always asserted one mclk period before the expected read data. Therefore, the timing of read_en changes as cas_latency is changed using the APB interface.

When the controller issues a Read command, after a delay of several mclk cycles it registers the data into the read data FIFO, see Figure 2.26. This delay is dependent on the delays in the legacy pad interface and the value programmed in the cas_latency Register.

Legacy pad interface to external memory devices

The legacy pad interface block registers the relevant command signals with clocks that enable the external memory device timing to be met.

It is expected that a Delay-Locked Loop (DLL) is required to delay the dqs_in_<n>, dqs_in_n_<n>, dqs_in_ecc and dqs_in_n_ecc signals coming back from the memories with respect to the dq_in data bus. The standard delay for the dqs_in_<n>, dqs_in_n_<n>, dqs_in_ecc and dqs_in_n_ecc signals is a quarter clock period of mclk. A DLL is not included in the DDR2 DMC. The asetbok signal enables DLLs to update at safe points in time. See Table A.4.

DFI pad interface

If the DDR2 DMC is configured to support DFI then it implements a DFI pad interface that complies with Version 2.0 of the DDR PHY Interface (DFI) Specification.

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