CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 2.1.1. AXI slave interface

2.1.1. AXI slave interface

The AXI slave interface comprises the following AXI channels:

Write address channel: Enables the transfer of the address and all other control data required for the DDR2 DMC to carry out an AXI write transaction.
Write data channel: Enables the transfer of write data and validating data byte strobes to the controller.
Write response channel: Enables the transfer of response information associated with a write transaction.
Read address channel: Enables the transfer of the address and all other control data required for the controller to carry out an AXI read transaction.
Read data channel: Enables the transfer of read data and response information associated with a read transaction.

See the AMBA AXI Protocol Specification for more information.

Figure 2.2 shows the AXI slave interface signals.

Note

In Figure 2.2 the arcache, awcache, arprot, and awprot signals are shown for completeness only. The controller ignores any information that these signals provide.

Figure 2.2. AXI slave interface signals

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