2.2.10. Memory interface

The memory interface of the DDR2 DMC is separated from the arbiter using the following configurable blocks:

The memory interface reads commands from the arbiter using the command FIFO but only when that command can be executed. The memory interface ensures a command is only executed when all the inter-command delays, defined in this section, for that bank or chip are met.

The memory interface enables multiple banks to be active at any one time. However, only one bank can be carrying out a data transfer at any one time. If the command at the head of the command FIFO cannot be executed, then the command pipeline stalls until it can be executed.

When the auto_power_down bit is set, see Memory Configuration Register, then the cke output signal is negated to take the external memories into active or precharge power-down depending on whether there is a row open. See Figure 2.23. When exiting power down mode, the delay before the next command is issued is programmed using the Exit Power-down Timing Register.

An mclk FSM controls the operation of the power-down mode. This FSM has a state that is entered when the DDR2 SDRAM is put into self-refresh mode. This is used so that if power is removed from all of the DDR2 DMC apart from the memory interface and pad interface, the state of the memory is known. When the rest of the controller is powered-up, the aclk FSM enters the Low_power state rather than the Config state.

Memory interface to pad interface timing

All command control outputs are clocked on the same edge of the memory clock, mclk.

The relative times between control signals from the memory interface are maintained when output from the pad interface to the actual DDR2 memory devices. Therefore, the timing register values required for a particular DDR2 SDRAM can be determined from that memory device’s data sheet.

Figure 2.14 to Figure 2.26 show how the data sheet timings map onto the DDR2 DMC timing registers. The timing registers are shown in Figure 3.2.

Note

In Figure 2.14 to Figure 2.26:

  • The following signals are internal to the DDR2 DMC:

    • command_en

    • data_cntl_en

    • memif_busy

    • pwr_down

    • read_en.

  • The control outputs to the external memory are always clocked on the falling edge of the memory clock, mclk.

  • The timings shown are not necessarily the default timing values but are values that are small enough to show the entire delay in one figure.

Figure 2.14 shows the command control output timing.

Figure 2.14. Command control output timing

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Figure 2.15 shows the ACTIVE command to Read or Write command timing, that you program using the ACTIVE to Read or Write Timing Register.

Figure 2.15. ACTIVE command to Read or Write command timing, tRCD

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Figure 2.16 shows the four activate window command timing, that you program using the Four Activate Window Timing Register.

Figure 2.16. Four activate window command timing, tFAW

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Figure 2.17 shows ACTIVE to ACTIVE on the same bank, and ACTIVE to AUTO REFRESH command timing, that you program using the ACTIVE to ACTIVE Timing Register.

Figure 2.17. Same bank ACTIVE to ACTIVE, and ACTIVE to AUTO REFRESH timing, tRC

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Figure 2.18 shows the ACTIVE to ACTIVE command timing to different memory banks, that you program using the ACTIVE to ACTIVE Different Bank Timing Register.

Figure 2.18. Different bank ACTIVE to ACTIVE command timing, tRRD

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Figure 2.19 shows the PRECHARGE to command, and AUTO REFRESH timing, that you program using the PRECHARGE to Command Timing Register and AUTO REFRESH to Command Timing Register.

Figure 2.19. PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC

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Figure 2.20 shows ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing, that you program using the ACTIVE to PRECHARGE Timing Register and PRECHARGE to Command Timing Register.

Figure 2.20. ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing, tRAS and tRP

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Figure 2.21 shows MODEREG to command timing, that you program using the MODEREG to Command Timing Register.

Figure 2.21. MODEREG to command timing, tMRD

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Figure 2.22 shows self-refresh entry and exit timing, that you program using the Self-refresh to Command Timing Register and Exit Self-refresh Timing Register.

Figure 2.22. Self-refresh entry and exit timing, tESR and tXSR

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Figure 2.23 shows power-down entry and exit timing, that you program using the Memory Configuration 3 Register and Exit Power-down Timing Register.

Figure 2.23. Power down entry and exit timing, tXP

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The power_dwn_prd count is timed from the memory interface becoming idle, that is, after a command delay has timed out or the read data FIFO is emptied. cke is asserted when the command FIFO is not empty.

Figure 2.24 shows the turnaround time, tWTR, for the memory interface to output a Write command followed immediately by a Read command. Program this value using the Write to Read Timing Register.

Figure 2.24. Data output timing, tWTR

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Figure 2.25 shows the relationship between the memory interface outputting a Write command and the write data, when CAS latency is set to 3, resulting in a write latency of 2. It also highlights the tWR minimum time between a Write and a PRECHARGE command, that you program using the Write to PRECHARGE Timing Register.

Figure 2.25. Data output timing, write latency = 2

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Figure 2.26 shows the timing relationship between a Read command being output from the memory interface and the read data being returned to the memory interface from the pad interface. Program this timing using the CAS Latency Register.

Figure 2.26. Data input timing

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