2.2.8. Memory manager

The memory manager tracks and controls the current state of the DDR2 DMC using the aclk Finite State Machine (FSM). You can change the state of the controller by programming the memc_cmd Register, see Memory Controller Command Register.

You can also use the AXI low-power interface to move the controller between the Ready and Low_power states, see Power-down support and usage model.

Figure 2.13 shows the aclk FSM.

Figure 2.13. aclk domain state diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

In Figure 2.13, non-state moving transitions are omitted for clarity. See Table 2.5 for valid system states.


  • If the controller receives an APB command that is illegal to carry out from the current state, then the controller ignores it and the aclk FSM stays in the same state.

  • For the two cycles following Power-On-Reset (POR), do not consider the controller to be in the Config state. For this reason, register access restrictions apply.

  • You can only use the AXI low-power interface to move in and out of the Low_power state from the Ready state.

  • If the controller enters the Low_power state using the:

    • APB interface then it must also exit the Low_power state using the APB interface

    • AXI low-power interface then it must also exit the Low_power state using the AXI low-power interface.

  • When the controller is in the Ready state it periodically issues AUTO REFRESH commands to the SDRAMs. When the controller is in the Config or Paused state it does not issue AUTO REFRESH commands unless software writes the appropriate command to the direct_cmd Register. However, this register is only accessible in the Config state and therefore software must limit the duration of the Paused state.

  • If you move the controller from the Low_power state to the Paused state then you must not move the controller immediately back to the Low_power state if it has not sent an AUTO REFRESH command. This is because, when a memory device exits self-refresh and then re-enters self-refresh mode, the JEDEC STANDARD DDR2 SDRAM Specification requires a controller to issue at least one AUTO REFRESH command.

The APB slave interface stalls the psel and penable signals using the pready signal if a previous command has not completed.

The memory manager issues commands from one of the following sources:

Direct commands

These are received over the APB interface as a result of a write to the direct_cmd Register, see Direct Command Register. Use these commands to initialize the DDR2 SDRAM and generate periodic refresh commands.

The legal commands that the memory manager uses are:

  • NOP




  • extended MODEREG.

Commands from the aclk FSM

You can traverse the aclk FSM by writing to the memc_cmd Register. See Memory Controller Command Register. You can only traverse the aclk FSM states when the DDR2 DMC is idle. For example, the Ready state can only be entered from the Config state when all direct commands have been completed. The eption to this is the Active_Pause command. You can issue this command when the controller is active. When you issue the command, any memory accesses that have not been arbitrated remain in the arbiter until the aclk FSM receives a Go command.

Refresh commands

The refresh logic can issue commands to the arbiter to refresh the DDR2 SDRAMs. The refresh rate period is programmable using the Refresh Period Register. The value of this register is the time period in mclk cycles that must occur before the memory manager requests the arbiter to generate an AUTO REFRESH command. This request is arbitrated and might not necessarily be initiated immediately. See Arbiter.

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E