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The DDR2 DMC provides support for low-power operation in the following ways:
By using the memory_cfg Register, the controller can automatically place a memory device into either the precharge power-down or active power-down states by deasserting cke when a memory device has been inactive for a number of clock cycles. This occurs with the controller in the Ready state. See Memory Configuration Register.
By using the memc_cmd and memc_status Registers, the controller can place the memory device into self-refresh mode under software control. See Memory Controller Status Register and Memory Controller Command Register.
By using the AXI low-power interface, the controller can place the memory device into self-refresh mode under hardware control.
Additionally, the controller provides additional power savings through extensive use of clock gating.
It is possible to implement the controller with two power domains:
APB and AXI, aclk
memory, mclk. Figure 2.12 shows these clock domains.
Table 2.5 shows the valid system states of the aclk FSM and an mclk FSM. It also shows the valid power, clock, and reset states in the aclk and mclk domains. Figure 2.27 shows the valid transitions, and the text following it explains how to traverse the system states.
Table 2.5. Valid system states for FSMs
| State | Memory device | DDR2 DMC aclk FSM | DDR2 DMC mclk FSM | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| VDD | State | VDD | Clock | Reset | State | VDD | Clock | Reset | State | |
| 1 | 0 | Null | 0 | - | - | Null | 0 | - | - | Null |
| 2 | 0 | Null | >0 | Running | No | POR | >0 | Running | No | POR |
| 3 | 0 | Null | >0 | Running | Yes | Reset | >0 | Running | Yes | Reset |
| 4 | 0 | Null | >0 | Running | No | Config | >0 | Running | No | Pwr_up |
| 5 | >0 | Accessible | >0 | Running | No | Config | >0 | Running | No | Pwr_up |
| 6 | >0 | Accessible | >0 | Running | No | Ready | >0 | Running | No | Pwr_up |
| 7 | >0 | Power-down | >0 | Running | No | Ready | >0 | Running | No | Pwr_down |
| 8 | >0 | Self-refresh | >0 | Running | No | Low_power | >0 | Running | No | Pwr_sref |
| 9 | >0 | Self-refresh | >0 | Running | No | Low_power | >0 | Stopped | No | Pwr_sref |
| 10 | >0 | Self-refresh | >0 | Stopped | No | Low_power | >0 | Running | No | Pwr_sref |
| 11 | >0 | Self-refresh | >0 | Stopped | No | Low_power | >0 | Stopped | No | Pwr_sref |
| 12 | >0 | Self-refresh | 0 | - | - | Null | >0 | Stopped | No | Pwr_sref |
| 13 | >0 | Self-refresh | 0 | - | - | Null | >0 | Running | No | Pwr_sref |
| 14 | >0 | Self-refresh | >0 | Running | No | POR | >0 | Stopped | No | Pwr_sref |
| 15 | >0 | Self-refresh | >0 | Running | No | POR | >0 | Running | No | Pwr_sref |
| 16 | >0 | Self-refresh | >0 | Running | Yes | Reset | >0 | Stopped | No | Pwr_sref |
| 17 | >0 | Self-refresh | >0 | Running | Yes | Reset | >0 | Running | No | Pwr_sref |
The ranking of system power states, from highest power to lowest power, is as follows:
6, 7, 8, 10, 9, 11, 13, 12.
However, states 8-11 are similar and the recommendation is to use state 11 from this group if clock-stopping techniques are available. Similarly, states 12 & 13 are similar and the recommendation is to use state 12 from this pair. Table 2.6 shows a recommended set of power states.
Table 2.6. Recommended power states
| System state | Power name |
|---|---|
| 6 | Running |
| 7 | Auto power-down |
| 11 | Shallow self-refresh |
| 12 | Deep self-refresh |
Figure 2.27 shows these system states and arcs.
States 1-5, 9, 14, and 16 are only used as transitional states.
The state transitions are:
Apply power to all DDR2 DMC power domains, and ensure that aclk and mclk are running.
Assert reset in the aclk reset domain and the mclk reset domain.
Deassert reset in the aclk reset domain and the mclk reset domain.
Apply power to the memory device power domain.
You must:
Program the DDR2 DMC timing registers with the timing parameters for the DDR2 SDRAM. Figure 3.2 shows the timing registers.
Write to the memory_cfg and refresh_prd Registers. See Memory Configuration Register and Refresh Period Register.
Initialize the memory, using the direct_cmd Register, with the sequence of commands specified by the memory vendor. See Direct Command Register and DDR2 device initialization.
When you have sent these commands to the memory, you can write to the memc_cmd Register with the Go command. See Memory Controller Command Register.
Poll the memc_status Register until the memc_status
field returns 0b01, signifying that the controller
is ready to accept AXI accesses to the memory devices.
If you want
to reconfigure either the controller or memory devices, you must
first write to the memc_cmd Register, with the Pause command, and
poll the memc_status Register until the memc_status field returns 0b10,
Paused.
Then you can write to the memc_cmd Register with the Configure
command, and poll the memc_status Register until the memc_status
field returns 0b00, Config. See Memory Controller Status Register and Memory Controller Command Register.
If auto_power_down is set in the memory_cfg Register then this arc is automatically taken when the SDRAM has been idle for power_dwn_prd mclk cycles. See Memory Configuration Register.
When an SDRAM access command has been received in the mclk domain, this arc is taken.
You can take this arc under either hardware or software control:
To take this arc under software control:
Issue the Pause command using the memc_cmd Register.
Poll the memc_status Register for the Paused state.
Issue the Sleep command using the memc_cmd Register.
To take this arc under hardware control, use the AXI low-power interface to request the Low_power state.
The same as arc 6 to 8 but also stops the mclk domain clock.
The same as arc 6 to 8 but also stops the aclk domain clock.
The same as arc 6 to 8 but also stop the mclk and the aclk domain clocks.
The same as arc 6 to 8 but also stops the mclk domain clock and removes power from the aclk power domain. This can only be done if the DDR2 DMC implementation has separate power domains for aclk and mclk.
The same as arc 6 to 8 but also removes power from the aclk power domain. This can only be done if the DDR2 DMC implementation has separate power domains for aclk and mclk.
You can take this arc under either hardware or software control:
To take this arc under software control:
Issue the Wakeup command using the memc_cmd Register.
Poll the memc_status Register for the Paused state.
Issue the Go command and poll for the Ready state.
To take this arc under hardware control, use the AXI low-power interface to bring the controller out of the Low_power state.
The same as arc 8 to 6 but you must first start the mclk domain clock.
The same as arc 8 to 6 but you must first start the aclk domain clock.
The same as arc 8 to 6 but you must first start the aclk and mclk domain clocks.
Apply power to the aclk power domain.
Assert reset to the aclk reset domain.
Deassert reset to the aclk reset domain.
Apply power to the aclk power domain.
Assert reset to the aclk reset domain.
Deassert reset to the aclk reset domain.
| Copyright © 2007, 2009-2010 ARM Limited. All rights reserved. | ARM DDI 0418E |
| Non-Confidential | ID080910 |
| PDF version | |
| Home > Functional Description > Functional operation > Power-down support and usage model |