2.2.13. Power-down support and usage model

The DDR2 DMC provides support for low-power operation in the following ways:

Additionally, the controller provides additional power savings through extensive use of clock gating.

It is possible to implement the controller with two power domains:

Table 2.5 shows the valid system states of the aclk FSM and an mclk FSM. It also shows the valid power, clock, and reset states in the aclk and mclk domains. Figure 2.27 shows the valid transitions, and the text following it explains how to traverse the system states.

Table 2.5. Valid system states for FSMs

StateMemory deviceDDR2 DMC aclk FSMDDR2 DMC mclk FSM
VDDStateVDDClockResetStateVDDClockResetState
10Null0--Null0--Null
20Null>0RunningNoPOR>0RunningNoPOR
30Null>0RunningYesReset>0RunningYesReset
40Null>0RunningNoConfig>0RunningNoPwr_up
5>0Accessible>0RunningNoConfig>0RunningNoPwr_up
6>0Accessible>0RunningNoReady>0RunningNoPwr_up
7>0Power-down>0RunningNoReady>0RunningNoPwr_down
8>0Self-refresh>0RunningNo Low_power>0RunningNoPwr_sref
9>0Self-refresh>0RunningNo Low_power>0StoppedNoPwr_sref
10>0Self-refresh>0StoppedNo Low_power>0RunningNoPwr_sref
11>0Self-refresh>0StoppedNo Low_power>0StoppedNoPwr_sref
12>0Self-refresh0--Null>0StoppedNoPwr_sref
13>0Self-refresh0--Null>0RunningNoPwr_sref
14>0Self-refresh>0RunningNoPOR>0StoppedNoPwr_sref
15>0Self-refresh>0RunningNoPOR>0RunningNoPwr_sref
16>0Self-refresh>0RunningYesReset>0StoppedNoPwr_sref
17>0Self-refresh>0RunningYesReset>0RunningNoPwr_sref

The ranking of system power states, from highest power to lowest power, is as follows:

6, 7, 8, 10, 9, 11, 13, 12.

However, states 8-11 are similar and the recommendation is to use state 11 from this group if clock-stopping techniques are available. Similarly, states 12 & 13 are similar and the recommendation is to use state 12 from this pair. Table 2.6 shows a recommended set of power states.

Table 2.6. Recommended power states

System statePower name
6Running
7Auto power-down
11Shallow self-refresh
12Deep self-refresh

Figure 2.27 shows these system states and arcs.

Figure 2.27. System state transitions

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Note

States 1-5, 9, 14, and 16 are only used as transitional states.

The state transitions are:

Arc 1 to 2

Apply power to all DDR2 DMC power domains, and ensure that aclk and mclk are running.

Arc 2 to 3

Assert reset in the aclk reset domain and the mclk reset domain.

Arc 3 to 4

Deassert reset in the aclk reset domain and the mclk reset domain.

Arc 4 to 5

Apply power to the memory device power domain.

Arc 5 to 6

You must:

  1. Program the DDR2 DMC timing registers with the timing parameters for the DDR2 SDRAM. Figure 3.2 shows the timing registers.

  2. Write to the memory_cfg and refresh_prd Registers. See Memory Configuration Register and Refresh Period Register.

  3. Initialize the memory, using the direct_cmd Register, with the sequence of commands specified by the memory vendor. See Direct Command Register and DDR2 device initialization.

    When you have sent these commands to the memory, you can write to the memc_cmd Register with the Go command. See Memory Controller Command Register.

  4. Poll the memc_status Register until the memc_status field returns 0b01, signifying that the controller is ready to accept AXI accesses to the memory devices.

Arc 6 to 5

If you want to reconfigure either the controller or memory devices, you must first write to the memc_cmd Register, with the Pause command, and poll the memc_status Register until the memc_status field returns 0b10, Paused.

Then you can write to the memc_cmd Register with the Configure command, and poll the memc_status Register until the memc_status field returns 0b00, Config. See Memory Controller Status Register and Memory Controller Command Register.

Arc 6 to 7

If auto_power_down is set in the memory_cfg Register then this arc is automatically taken when the SDRAM has been idle for power_dwn_prd mclk cycles. See Memory Configuration Register.

Arc 7 to 6

When an SDRAM access command has been received in the mclk domain, this arc is taken.

Arc 6 to 8

You can take this arc under either hardware or software control:

  • To take this arc under software control:

    1. Issue the Pause command using the memc_cmd Register.

    2. Poll the memc_status Register for the Paused state.

    3. Issue the Sleep command using the memc_cmd Register.

  • To take this arc under hardware control, use the AXI low-power interface to request the Low_power state.

Arc 6 to 9

The same as arc 6 to 8 but also stops the mclk domain clock.

Arc 6 to 10

The same as arc 6 to 8 but also stops the aclk domain clock.

Arc 6 to 11

The same as arc 6 to 8 but also stop the mclk and the aclk domain clocks.

Arc 6 to 12

The same as arc 6 to 8 but also stops the mclk domain clock and removes power from the aclk power domain. This can only be done if the DDR2 DMC implementation has separate power domains for aclk and mclk.

Arc 6 to 13

The same as arc 6 to 8 but also removes power from the aclk power domain. This can only be done if the DDR2 DMC implementation has separate power domains for aclk and mclk.

Arc 8 to 6

You can take this arc under either hardware or software control:

  • To take this arc under software control:

    1. Issue the Wakeup command using the memc_cmd Register.

    2. Poll the memc_status Register for the Paused state.

    3. Issue the Go command and poll for the Ready state.

  • To take this arc under hardware control, use the AXI low-power interface to bring the controller out of the Low_power state.

Arc 9 to 6

The same as arc 8 to 6 but you must first start the mclk domain clock.

Arc 10 to 6

The same as arc 8 to 6 but you must first start the aclk domain clock.

Arc 11 to 6

The same as arc 8 to 6 but you must first start the aclk and mclk domain clocks.

Arc 12 to 14

Apply power to the aclk power domain.

Arc 14 to 16

Assert reset to the aclk reset domain.

Arc 16 to 9

Deassert reset to the aclk reset domain.

Arc 13 to 15

Apply power to the aclk power domain.

Arc 15 to 17

Assert reset to the aclk reset domain.

Arc 17 to 8

Deassert reset to the aclk reset domain.

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