2.1.7. Memory interface

The memory interface provides a clean and defined interface between the pad interface and the arbiter, ensuring that the external memory interface command protocols are met in accordance with the programmed timings in the register block. See Chapter 3 Programmers Model.

The external inputs and outputs to this block are:


Clock for mclk domain.


Reset for mclk domain. This signal is active LOW.

The memory interface tracks and controls the state of an external memory by using an mclk FSM. See Figure 2.8.

Figure 2.8. mclk domain state diagram

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See Table 2.5 for valid system states.

See Memory interface for more information.

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