2.2.7. Arbiter

The arbiter receives memory access commands from the AXI slave interface and the memory manager. It passes the highest priority command to the memory interface after arbitration. Read data is passed from the memory interface to the AXI slave interface.

This section describes:

Formatting from memory manager

The direct command uses the chip select bits [21:20] in the direct_cmd Register to select the required memory chip. See Direct Command Register.

The command to be carried out is either:

  • a self-refresh request from the AXI-C interface

  • an auto-refresh

  • a direct command from the APB interface.

It is encoded by the memory manager to match the format that the arbiter requires.

Arbiter access multiplexor

The selection of a command from the AXI slave interface or the memory manager is fixed, with the memory manager having a higher priority.

The selection between an AXI read access and AXI write access is made using a round-robin arbitration, unless a read access has a low latency QoS value, or if any of the accesses are to a row already open. See Arbitration algorithm for more information.

See also Formatting from AXI address channels. In this case, it is arbitrated immediately.

Hazard detection

The following types of hazard exist:

Read After Read (RAR)

There is a read already in the arbiter queue with the same ID as the incoming entry, that is also a read.

Write After Write (WAW)

There is a write already in the arbiter queue with the same ID as the incoming entry, that is also a write.

Read After Write (RAW)

There is a write in the arbiter queue, that has received an early write response, accessing the same location as the incoming read entry.

The arbiter entry is flagged as having a dependency if a hazard is detected. There might be dependencies against a number of other arbiter entries. As the arbiter entries are invalidated, so the dependencies are reduced until finally, there are no outstanding dependencies, and the entry is free to start.


There are no Write-After-Read (WAR) hazard checks in the DDR2 DMC. If an AXI master requires ordering between reads and writes to certain memory locations, it must wait for read data before issuing a write to a location it has read from. Similarly, the only RAW hazard checking is that performed when the write response has been issued. If an AXI master required ordering between writes and reads to certain memory locations, it must wait for the write response before issuing the read to the same location.


The scheduler monitors the activity of the mclk FSMs in the memory interface. This enables the arbiter to select an entry from the queue that does not stall the memory pipeline.

Quality of Service

Quality of Service (QoS) is defined for the DDR2 DMC as a method of increasing the arbitration priority of a read access that requires low-latency read data. The QoS for an AXI read access is determined when it is received by the arbiter.

There is no QoS for write accesses. However, any write access that is a dependency for a QoS read access receives a promoted priority to complete as soon as possible. Dependencies are formed based on the hazard detection logic that Hazard detection describes.

The following sections describe:

QoS selection

The DDR2 DMC selects the QoS for an AXI read transfer by masking the arid with a 4-bit QoS mask. You can program the QoS mask to be either arid[3:0], arid[4:1], arid[5:2], arid[6:3], arid[7:4], arid[8:5], arid[9:6], or arid[10:7] by using the qos_master_bits in the memory_cfg Register. After the controller applies the QoS mask to the four specified arid bits, the resulting value <n> provides the pointer to which id_<n>_cfg Register contains the QoS settings for the read transfer. See Memory Configuration Register and QoS Configuration Registers.

Example 2.2 shows QoS selection and the impact of the qos_override signal.

Example 2.2. QoS selection and qos_override

If you program the qos_master_bits = 0b010 then this selects arid[5:2] to be the 4-bit QoS mask. If the DDR2 DMC receives an AXI transfer with an arid of 0x5A then it applies the 4-bit QoS mask, arid[5:2], giving a value of 0x6. Therefore, the controller uses the id_6_cfg Register to control the QoS for the transfer.

The controller creates a new arbiter entry for the transfer and assigns it the qos_min and qos_max values from the id_6_cfg Register. If the qos_enable bit = 1 then the controller applies the QoS settings to the transfer.

The qos_override[15:0] signal enables the controller to assign an arbiter entry with minimum QoS latency, irrespective of the state of the qos_enable bit. For this example, if qos_override[6] is HIGH when arvalid and arready are HIGH then the arbiter entry is assigned minimum QoS latency, even if the qos_enable bit = 0.

QoS timeout

If the qos_enable bit is set then the arbiter decrements the QoS maximum latency value every aclk cycle until it reaches zero. If the entry is still in the queue when the QoS maximum latency value reaches zero, then the entry becomes high priority. This is called a timeout. Also, any entry in the queue with a minimum latency QoS also produces a timeout. Minimum latency timeouts have priority over maximum latency timeouts.

When an entry times out in this way it forces a timeout onto any entries that it has dependencies against. In normal operation, these entries have already timed out because they have received the same initial QoS value but been decrementing for longer. The highest priority arbiter entry is serviced next.

One special case exists. This is when or if the assertion of the relevant qos_override signal forces a minimum latency timeout. In this instance, any accesses that the new entry has dependencies against might not have timed out and are forced to time out so that the high-priority entry can start as soon as possible.


The DDR2 DMC provides QoS for the AUTO REFRESH commands by using a simple increment-decrement counter for each memory device. The counter tracks the number of AUTO REFRESH commands in the arbiter queue and when it reaches a value of six then a refresh timeout is signaled to the arbiter queue.

A refresh timeout forces all of the AUTO REFRESH queue entries to timeout. This timeout is sticky, and does not disappear when the number of timeouts drops below six. Instead, it remains asserted until the controller services all of the AUTO REFRESH entries. This provides a guaranteed refresh rate in the SDRAM.

Arbitration algorithm

The ordering of commands to be carried out from the arbiter queue is arbitrated with a priority scheme of the following order:

  • refresh timeouts

  • minimum latency timeouts

  • maximum latency timeouts

  • open-row hits in the same direction

  • open-row hits in the opposite direction

  • preparation operations

  • refreshes.


Preparation operations can be interleaved between memory operations to other banks to improve memory interface utilization.

Command formatting

For every memory burst access necessary to complete an arbiter queue entry, a memory interface command is required.

Command formatting calculates the number of memory interface commands and memory cycles for each command to complete the next arbiter queue entry that is to be sent to the memory interface. It contains an address incrementer and a beat decrementer so that the arbiter entry can be interrupted and restarted.

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