2.2.2. AXI slave interface

The AXI programmer’s view is of a flat area of memory. The full range of AXI operations are supported.

The base addresses of the external memory devices are programmable using the chip_cfg<n> Registers. See Chip Configuration Registers.

In addition to reads and writes, exclusive reads and writes are supported in accordance with the AMBA AXI Protocol Specification. Successful exclusive accesses have an EXOKAY response. All other accesses, including exclusive fail accesses, receive an OKAY response.

Note

Refreshes can be missed if rready is held LOW for longer than one refresh period and the read data FIFO, command FIFO, and arbiter queue become full. An OVL error is triggered if this occurs in simulation. Ensure that the DDR2 DMC has a sufficiently high system priority to prevent this.

This section describes:

Configuration options

You can choose 128-bit, 64-bit, or 32-bit data width.

Write data merging

The DDR2 DMC merges interleaved write data to optimize the utilization of the memory interface.

Early BRESP

To enable early write response timing, the DDR2 DMC employs write data buffering and issues the BRESP transfer before the data has been committed to the DDR2 SDRAM. The response is sent after the last data beat is accepted by the AXI slave interface and stored in the write data buffer. You can disable this feature using the Feature Control Register.

Note

For exclusive write accesses, the controller only issues a BRESP transfer after the write transaction is committed to a memory device.

AXI slave interface attributes

Table 2.1 shows the AXI slave attributes and their values.

Table 2.1. AXI slave interface attributes

Attribute [a]Value
Combined acceptance capabilityArbiter queue depth
Write interleave depthCombined acceptance capability
Read data reorder depthCombined acceptance capability

[a] SeeGlossary for a description of these AXI attributes.


Formatting from AXI address channels

Formatting is as follows:

Chip select decoding

Using the programmed values in the chip_cfg<n> Registers, see Chip Configuration Registers, that Chapter 3 Programmers Model defines, an incoming address has the most significant eight address bits compared with the address match bits using the address mask to ignore any don't care bits to select an external chip.

The transfer is still carried out if there is no match, but the result is undefined.

Row select decoding

The row address is determined from the AXI address using bits [5:3] of the memory_cfg Register, and also the brc_n_rbc bit for the selected chip defined in the chip_cfg<n> Register. See Memory Configuration Register and Chip Configuration Registers.

Column select decoding

The column address is determined from the AXI address using bits [2:0] of the memory_cfg Register. See Memory Configuration Register.

Bank select decoding

The chip bank is determined from the AXI address using bits [5:3] of the memory_cfg2 Register, and also the brc_n_rbc bit for the selected chip defined in the chip_cfg<n> Register. See Memory Configuration 2 Register and Chip Configuration Registers.

Number of beats

The number of memory beats is determined, depending on the effective external memory width and the burst size of the AXI access. AXI wrapping bursts are split into two incrementing bursts. AXI fixed bursts are split into AXI burst length memory bursts.

Note

On the memory interface, the DDR2 DMC supports a burst length of four or eight.

Exclusive access

In addition to reads and writes, the DDR2 DMC supports exclusive reads and writes in accordance with the AMBA AXI Protocol Specification.

Successful exclusive accesses have an EXOKAY response. All other accesses, including exclusive fail accesses, receive an OKAY response.

Exclusive access monitors implement the exclusive access functionality. Each monitor can track a single exclusive access. The number of monitors is a configurable option.

If an exclusive write fails, the data mask for the write is forced LOW, so the data is not written.

When monitoring an exclusive access, the address of any write from another master is compared with the monitored address to check that the location is not being updated.

For the purposes of monitoring, address comparison uses a bit mask derived as follows:

Consider the byte addresses accessed by a transaction. All of the least significant bits up to and including the most significant bit that vary between those addresses are set to logic zero in the mask. All of the stable address bits above this point are set to 0b1.

Example 2.1 provides information about three transactions.

Example 2.1. Exclusive accesses

Exclusive Read

Address = 0x000, size = WORD, length = 1, ID = 0.

Write

Address = 0x004, size = WORD, length = 2, ID = 1.

Exclusive Write

Address = 0x000, size = WORD, length = 1, ID = 0.


The write transaction accesses the address range 0x104-0x10B and address bit 3 is the most significant bit that varies between byte addresses. Because address bits 3 down to 0 are not compared, the monitoring logic calculates as if the masked write has accessed the monitored address and marks the exclusive write as a failure.

Table 2.2 shows the address comparison steps.

Table 2.2. Address comparison steps example

Step BinaryHex
1Monitored address0b0001 0000 00000x100
2Write address0b0001 0000 01000x104
3Write accesses0b0001 0000 01000x104
0b0001 0000 01010x105
0b0001 0000 01100x106
0b0001 0000 01110x107
0b0001 0000 10000x108
0b0001 0000 10010x109
0b0001 0000 10100x10A
0b0001 0000 10110x10B
4Generate a comparison mask0b1111 1111 00000xFF0
5Monitored address ANDed with mask0b0001 0000 00000x100
6Write address ANDed with mask0b0001 0000 00000x100
7Compare steps 5 and 6  
8Mark exclusive write as failed  

This example shows how the logic can introduce false negatives in exclusive access monitoring, because in reality the write does not access the monitored address. The implementation is chosen to reduce design complexity but always provide safe behavior.

When calculating the address region accessed by the write, the burst type is always taken to be INCR. Therefore, a wrapped transaction in Example 2.1 that wraps down to 0x0 rather than cross the boundary, is treated in the same way. This is the same for a fixed burst that does not cross the boundary or wrap down to 0x0.

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