CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual: 2.2.1. Clocking and resets

2.2.1. Clocking and resets

This section describes:

Clocking

The DDR2 DMC has the following functional clock inputs:

aclk
mclk
mclkn
mclkx2
mclkx2n
dqs_in_<n> where n is 0<n<bytes of external memory data bus
dqs_in_n_<n> where n is 0<n<bytes of external memory data bus.

Note

mclkn, mclkx2, mclkx2n, dqs_in_<n>, and dqs_in_n_<n> are only available if the controller is configured to contain a legacy pad interface.

These clocks can be grouped into two clock domains:

aclk domain: aclk is in this domain. The aclk domain signals can only be stopped if the external memories are put in self-refresh mode.
mclk domain: All clocks except aclk are in this domain. The mclk signal must be clocked at the rate of the external memory clock speed. The mclk domain signals can only be stopped if the external memories are put in self-refresh mode.

Note

If the controller contains a legacy pad interface then it provides a separate clock output for every memory device. If the controller contains a DFI pad interface then it asserts dfi_dram_clk_disable[MEMORY_CHIPS-1:0], to the DFI PHY, to disable the clock to a memory device.

Reset

The DDR2 DMC has two reset inputs:

aresetn: This is the reset signal for the aclk domain.
mresetn: This is the reset signal for the mclk domain.

You can change both reset signals asynchronously to their respective clock domain. Internally to the controller, the deassertion of the aresetn signal is synchronized to aclk, and the deassertion of the mresetn signal is synchronized to:

mclk for a DDR2 DMC configured with DFI
the mclk, mclkn, mclkx2, and mclkx2n clock signals for a DDR2 DMC configured with a legacy pad interface.

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