2.2.4. APB slave interface

The APB slave interface is a fully compliant APB slave. See the AMBA 3 APB Protocol Specification for information about an APB slave interface.

The APB interface enables you to access the operating state of the DDR2 DMC and to program it with the correct timings and settings for the connected memory type. See Chapter 3 Programmers Model for more information. The APB interface also initializes the connected memory devices, see Initialization.


The APB only supports single-word 32-bit accesses. The DDR2 DMC ignores paddr[1:0], resulting in byte and halfword accesses being treated as word accesses.

The APB interface is clocked by the same clock as the AXI domain clock, aclk. The controller provides a clock enable, pclken, enabling the APB interface to be slowed down and execute at an integer divisor of aclk.

To enable a clean registered interface to the external infrastructure, the APB interface always adds a wait state for all reads and writes by driving pready LOW. In the following instances, a delay of more than one wait state can be generated when a:

The only registers that can be accessed when the controller is not in the Config or Low_power state are:

To guarantee no missed AUTO REFRESH commands, it is recommended that any change of mclk period, and therefore update of the refresh period, is carried out when the controller is in the Low_power state. This is because the refresh rate depends on the mclk period. Only write direct commands to the external memories when the controller is in the Config state and not in the Low_power state.

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