2.2.12. Initialization

Before you can use the DDR2 DMC operationally to access external memory, you must:

You might not have to configure all of the DDR2 DMC registers because some might power-up to the correct value.

Note

A deadlock situation might occur if an AXI master accesses the AXI slave interface before a master has programmed the DDR2 DMC using the APB interface. Before the controller has been initialized, if a master can access the AXI slave interface but cannot access the APB interface, then that master must be held off until another master programs the controller.

The following sections provide examples of:

Controller initialization example

Table 2.3 shows an example initialization programming sequence for the controller.

Table 2.3. Controller initialization example

Register

Write dataDescription
cas_latency0x00000006Set CAS latency to 3
t_mrd0x00000002Set tMRD to 2
t_ras0x00000008Set tRAS to 8
t_rc0x0000000BSet tRC to 11
t_rcd0x00000103Set tRCD to 3 and schedule_rcd to 1
t_rfc0x00001315Set tRFC to 21 and schedule_rfc to 19
t_rp0x00000103Set tRP to 3 and schedule_rp to 1
t_rrd0x00000002Set tRRD to 2
t_wr0x00000003Set tWR to 3
t_wtr0x00000002Set tWTR to 2
t_xp0x00000002Set tXP to 2
t_xsr0x000000C8Set tXSR to 200
t_esr0x00000003Set tESR to 3
t_rddata_en0x00000003Set trddata_en to 3 if the DDR2 DMC is configured with a DFI pad interface

memory_cfg

0x0001A411

Sets the following memory configuration:

  • 9 column bits, 13 row bits

  • power-down period of 0

  • disable auto power-down

  • disable dynamic clock stopping

  • memory burst size of 4

  • use arid[5:2] bits for QoS

refresh_prd0x00000618Set an auto-refresh period of 3.9µs, that is, every 1560 (or 0x618) mclk periods when mclk frequency is 400MHz
memory_cfg20x00000001

Sets the following memory configuration:

  • aclk and mclk are synchronous

  • dqm[MEMORY_BYTES-1:0] are LOW at reset

  • cke is LOW at reset

  • two bits for the bank address

  • 16-bit data bus

chip_cfg00x000000FFSets address for chip 0 to be 0x00XXXXXX, Row Bank Column (RBC) configuration
chip_cfg10x000022FFSets address for chip 1 to be 0x22XXXXXX, RBC configuration
chip_cfg20x000055FFSets address for chip 2 to be 0x55XXXXXX, RBC configuration
chip_cfg30x00007FFFSets address for chip 3 to be 0x7FXXXXXX, RBC configuration
Wait 200µs to enable the memory devices to stabilize
direct_cmd-Sequence of writes to initialize the memory devices, see Table 2.4
memc_cmd0x00000000Change DDR2 DMC to the Ready state
memc_status-Poll the register until the memc_status field returns 0b01, signifying that the controller is ready to accept AXI accesses to the memory devices

DDR2 device initialization

Table 2.4 shows an example programming sequence for DDR2 device initialization. See the JEDEC STANDARD DDR2 SDRAM Specification for more information.

Table 2.4. DDR2 device initialization

Register

Write dataDescription
direct_cmd0x000C0000NOP command to chip 0.
Wait 400ns
direct_cmd0x00000000PRECHARGEALL command to chip 0.
direct_cmd0x000A0000MODEREG command to extended mode register 2, with low address bits = 0x0.
direct_cmd0x000B0000MODEREG command to extended mode register 3, with low address bits = 0x0.
direct_cmd0x00090000MODEREG command to extended mode register 1, with low address bits = 0x0, to enable the DLL.
direct_cmd0x00080132MODEREG command to mode register, with low address bits = 0x0132. This resets the DLL, burst length = 4, sequential bursts, CAS latency = 3.
direct_cmd0x00000000PRECHARGEALL command to chip 0.
direct_cmd0x00040000AUTO REFRESH command to chip 0.
direct_cmd0x00040000AUTO REFRESH command to chip 0.
direct_cmd0x00080032MODEREG command to mode register, with low address bits = 0x0032. DLL is active, and sets burst length = 4, sequential bursts, CAS latency = 3.
Wait for 200 mclk periods
direct_cmd0x00090380MODEREG command to extended mode register 1, with low address bits = 0x380, to set OCD calibration default.
direct_cmd0x00090000MODEREG command to extended mode register 1, with low address bits = 0x0, to exit OCD.

If a configured DDR2 DMC supports more than one memory chip then repeat the sequence in Table 2.4 but update the chip_addr field, in the direct_cmd Register, to select each additional memory chip. See Direct Command Register.

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