3.2. Register summary

Table 3.1 shows the DDR2 DMC registers in base offset order.

Table 3.1. DDR2 DMC register summary

OffsetNameTypeResetDescription
0x000memc_statusRO-[a]Memory Controller Status Register
0x004memc_cmdWO-Memory Controller Command Register
0x008direct_cmdWO-Direct Command Register
0x00Cmemory_cfgRW0x00010021Memory Configuration Register
0x010refresh_prdRW0x000001E7Refresh Period Register
0x014cas_latencyRW0x0000000ACAS Latency Register
0x018write_latencyRO0x00000004Write Latency Register
0x01Ct_mrdRW0x00000002MODEREG to Command Timing Register
0x020t_rasRW0x0000000EACTIVE to PRECHARGE Timing Register
0x024t_rcRW0x00000012ACTIVE to ACTIVE Timing Register
0x028t_rcdRW0x00000205ACTIVE to Read or Write Timing Register
0x02Ct_rfcRW0x00002023AUTO REFRESH to Command Timing Register
0x030t_rpRW0x00000205PRECHARGE to Command Timing Register
0x034t_rrdRW0x00000004ACTIVE to ACTIVE Different Bank Timing Register
0x038t_wrRW0x00000005Write to PRECHARGE Timing Register
0x03Ct_wtrRW0x00000004Write to Read Timing Register
0x040t_xpRW0x00000002Exit Power-down Timing Register
0x044t_xsrRW0x00000027Exit Self-refresh Timing Register
0x048t_esrRW0x00000014Self-refresh to Command Timing Register
0x04Cmemory_cfg2RW-[a]Memory Configuration 2 Register
0x050memory_cfg3RW0x00000007Memory Configuration 3 Register
0x054t_fawRW0x00001114Four Activate Window Timing Register
0x058update_type [b]RW0x00000000Update Type Register
0x05Ct_rddata_en [b]RW0x00000000Read Data Enable Timing Register
0x060t_wrlat_diff [b]RW0x00000000Write Data Enable Timing Register
0x064 - 0x0FC---Reserved, read undefined, write as zero
0x100 - 0x13Cid_<n>_cfgRW0x00000000QoS Configuration Registers
0x140 - 0x1FC---Reserved, read undefined, write as zero

0x200

0x204 [c]

0x208 [c]

0x20C [c]

chip_cfg0

chip_cfg1

chip_cfg2

chip_cfg3

RW

0x0000FF00

Chip Configuration Registers

0x210 - 0x2FC---Reserved, read undefined, write as zero
0x300user_statusRO-User Status Register
0x304user_config0WO-User Config 0 Register
0x308user_config1WO-User Config 1 Register
0x30Cfeature_ctrlRW0x00000000Feature Control Register
0x310 - 0x4FC---Reserved, read undefined, write as zero
0x500ecc_control [d]RW0x00000000ECC Control Register
0x504ecc_int_clr [d]WO-ECC Interrupt Clear Register
0x508ecc_status [d]RO0x00000000ECC Status Register
0x50Cecc_info0 [d]RO0x00000000ECC Information Register
0x510 - 0xDFC---Reserved, read undefined, write as zero

0xE00

0xE04

0xE08

int_cfg

int_inputs

int_outputs

See Chapter 4 Programmers Model for Test for more information about these registers

0xE0C - 0xFDC---Reserved, read undefined, write as zero
0xFE0 - 0xFECperiph_id_nRO0x00_41341 [e]Peripheral Identification Registers
0xFF0 - 0xFFCpcell_id_nRO0xB105F00DCoreLink Identification Registers

[a] Dependent on configuration.

[b] This register is only present when the DDR2 DMC is configured to implement a DDR PHY Interface (DFI), otherwise reads are undefined, write as zero.

[c] The presence of this register depends on the number of chip selects that a configured controller supports. If a controller does not implement the register then reads are undefined, write as zero.

[d] This register is only present when the DDR2 DMC is configured to support ECC, otherwise reads are undefined, write as zero.

[e] Dependent on the revision of the DDR2 DMC, see Peripheral Identification Register 2.


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