3.3.37. CoreLink Identification Registers

The pcell_id_[3:0] Register characteristics are:

Purpose

When concatenated, these four registers return 0xB105F00D to indicate that the DDR2 DMC is a CoreLink peripheral.

Usage constraints

No usage constraints.

Configurations

Available in all configurations of the DDR2 DMC.

Attributes

See the register summary in Table 3.1.

These registers can be treated conceptually as a single register that holds a 32-bit CoreLink identification value. You can use the register for automatic BIOS configuration.

Figure 3.44 shows the register bit assignments.

Figure 3.44. pcell_id Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.42 shows the register bit assignments.

Table 3.42. pcell_id Register bit assignments

pcell_id Registerpcell_id_[3:0] Registers
BitsReset valueRegisterBitsDescription
[31:24]0xB1pcell_id_3[31:8]Read undefined
[7:0]Returns 0xB1
[23:16]0x05pcell_id_2[31:8]Read undefined
[7:0]Returns 0x05
[15:8]0xF0pcell_id_1[31:8]Read undefined
[7:0]Returns 0xF0
[7:0]0x0Dpcell_id_0[31:8]Read undefined
[7:0]Returns 0x0D

Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.ARM DDI 0418E
Non-ConfidentialID080910