The QoS scheme works by reserving a number of slots in a slave’s combined acceptance capability queue for the exclusive use by particular masters.

The QoS scheme only provides support for slaves that have a combined acceptance capability, such as the PrimeCell Dynamic Memory Controller (PL340).

The QoS scheme has no effect until the AXI bus matrix calculates that, at a particular master interface, there are a number of unused slots equal to the value stored in the QoS tidemark register. It then accepts transactions only from slave ports specified in the QoS access control register. This restriction remains until the remaining number of slots again exceeds the value stored in the QoS tidemark register. See QoS tidemark register and QoS access control register.

Figure 2.2 shows the implementation for an interconnect that supports two masters and one slave.

See Programmable Quality of Service (ProgQoS) for more information.