configurable number of slave and master interfaces

multi-layer AXI routing, suitable for high-performance applications

sparse connection options to reduce gate count and improve security

configurable AXI data widths

configurable AHB-Lite data widths

configurable address widths on AXI and AHB-Lite interfaces

support for an AHB-Lite to AXI bridge optimized for use with memory controllers

support for AMBA 2 APB and AMBA 3 APB at 32-bit data width

decoded address register that you can configure for each slave interface

flexible register stages to aid timing closure

programmable, configurable arbitration that implements:

a programmable Quality of Service (QoS) scheme

an APB interface to provide access to programming registers

support for multiple clock domains:

configurable cyclic dependency schemes to enable a master to have outstanding transactions to more than one slave

PrimeCell ID register to aid self-discovery in systems

a configurable memory map

TrustZone support

AXI and AHB USER signal support

auto-generated Verilog

auto-generated RTL testbench

AMBA Designer tool based configuration.