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Table 3.1 lists the PL301 registers.
Table 3.1. PL301 register summary
| Address | Type | Width | Reset value | Name | Description |
|---|---|---|---|---|---|
0x00-0x3E0[1] | R/W | 8 | Configured[2] | Arbitration Control register for slave interfaces 0-31 | See Arbitration |
0x400[3] | R/W | 32 | 0x00000000 | QoS Tidemark for master interface 0 | See Programmable Quality of Service (ProgQoS) |
0x404[4] | R/W | 32 | 0x00000000 | QoS Access Control for master interface 0 | |
0x420-0x7FC | R/W | 32 | 0x00000000 | QoS Tidemark and Access Control for master interface 1-n | |
0x800-0xFBC | - | - | - | Reserved | - |
0xFC0 | RO | 32 | 0x000000nn[5] | PrimeCell Configuration Register 0 | See Configuration registers |
0xFC4 | RO | 32 | 0x000000nn[6] | PrimeCell Configuration Register 1 | |
0xFC8 | RO | 32 | 0x00000000 | PrimeCell Configuration Register 2 | |
0xFCC | RO | 32 | 0x00000000 | PrimeCell Configuration Register 3 | |
0xFD0-0xFDC | - | - | - | Reserved | |
0xFE0 | RO | 8 | 0x00 | PrimeCell Peripheral Register 0 | See PrimeCell Peripheral ID Registers 0-3 |
0xFE4 | RO | 8 | 0x14 | PrimeCell Peripheral Register 1 | |
0xFE8 | RO | 8 | 0x13 | PrimeCell Peripheral Register 2 | |
0xFEC | RO | 8 | 0x01 | PrimeCell Peripheral Register 3 | |
0xFF0 | RO | 8 | 0x0D | PrimeCell ID Register 0 | See PrimeCell ID Registers 0-3 |
0xFF4 | RO | 8 | 0xF0 | PrimeCell ID Register 1 | |
0xFF8 | RO | 8 | 0x05 | PrimeCell ID Register 2 | |
0xFFC | RO | 8 | 0xB1 | PrimeCell ID Register 3 | |
[1] Address allocation for arbitration control registers is [2] The arbitration control register reset value is dependent on the configured value set by AMBA Designer. See the AMBA Designer (FD001) User Guide for more information. [3] Address
allocation for QoS Tidemark is [4] Address
allocation for QoS Access Control is [5] Where
nn is the number of slave interfaces configured in the range [6] Where
nn is the number of master interfaces configured in the range | |||||