Glossary

This glossary describes some of the terms used in technical documents from ARM.

Advanced eXtensible Interface (AXI)

A bus protocol that supports separate address/control and data phases, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels to enable low-cost DMA, ability to issue multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure.The AXI protocol also includes optional extensions to cover signaling for low-power operation.

AXI is targeted at high-performance, high clock frequency system designs and includes a number of features that make it very suitable for high speed sub-micron interconnect.

Advanced High-performance Bus (AHB)

A bus protocol with a fixed pipeline between address/control and data phases. It only supports a subset of the functionality provided by the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM recommends only a subset of the protocol is usually used. This subset is defined as the AMBA AHB-Lite protocol.

See Also Advanced Microcontroller Bus Architecture and AHB-Lite.

Advanced Microcontroller Bus Architecture (AMBA)

A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that describes a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules.

Advanced Peripheral Bus (APB)

A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption.

AHB

See Advanced High-performance Bus.

AHB-Lite

A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA AHB interface are implemented more efficiently by using an AMBA AXI protocol interface.

Aligned

A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively.

AMBA

See Advanced Microcontroller Bus Architecture.

APB

See Advanced Peripheral Bus.

Architecture

The organization of hardware and/or software that characterizes a processor and its attached components, and enables devices with similar characteristics to be grouped together when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv6 architecture.

AXI

See Advanced eXtensible Interface.

AXI channel order and interfaces

The block diagram shows:

  • the order in which AXI channel signals are described

  • the MI and SI conventions for AXI components.

AXI terminology

The following AXI terms are general. They apply to both masters and slaves:

Active read transaction

A transaction for which the read address has transferred, but the last read data has not yet transferred.

Active transfer

A transfer for which the xVALID handshake has asserted, but for which xREADY has not yet asserted.

Note

The letter x in the signal name denotes an AXI channel as follows:

AW

Write address channel.

W

Write data channel.

B

Write response channel.

AR

Read address channel.

R

Read data channel.

Active write transaction

A transaction for which the write address or leading write data has transferred, but the write response has not yet transferred.

Completed transfer

A transfer for which the xVALID/xREADY handshake is complete.

Payload

The non-handshake signals in a transfer.

Transaction

An entire burst of transfers, comprising an address, one or more data transfers and a response transfer (writes only).

Transmit

An initiator driving the payload and asserting the relevant xVALID signal.

Transfer

A single exchange of information. That is, with one xVALID/xREADY handshake.

The following AXI terms are MI attributes. To obtain optimum performance, they must be specified for all components with an AXI MI:

Combined issuing capability

The maximum number of active transactions that an MI can generate. This is specified instead of write or read issuing capability for MIs that use a combined storage for active write and read transactions.

Read ID capability

The maximum number of different ARID values that an MI can generate for all active read transactions at any one time.

Read ID width

The number of bits in the ARID bus.

Read issuing capability

The maximum number of active read transactions that an MI can generate.

Write ID capability

The maximum number of different AWID values that an MI can generate for all active write transactions at any one time.

Write ID width

The number of bits in the AWID and WID buses.

Write interleave capability

The number of active write transactions for which the MI is capable of transmitting data. This is counted from the earliest transaction.

Write issuing capability

The maximum number of active write transactions that an MI can generate.

The following AXI terms are SI attributes. To obtain optimum performance, they must be specified for all components with an AXI SI

Combined acceptance capability

The maximum number of active transactions that an SI can accept. This is specified instead of write or read acceptance capability for SIs that use a combined storage for active write and read transactions.

Read acceptance capability

The maximum number of active read transactions that an SI can accept.

Read data reordering depth

The number of active read transactions for which an SI can transmit data. This is counted from the earliest transaction.

Write acceptance capability

The maximum number of active write transactions that an SI can accept.

Write interleave depth

The number of active write transactions for which the SI can receive data. This is counted from the earliest transaction.

Halfword

A 16-bit data item.

Multi-layer

An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a direct link to each slave, The link is not shared with other masters. This enables each master to process transfers in parallel with other masters. Contention only occurs in a multi-layer interconnect at a payload destination, typically the slave.

Processor

A processor is the circuitry in a computer system required to process data using the computer instructions. It is an abbreviation of microprocessor. A clock source, power supplies, and main memory are also required to create a minimum complete working computer system.

Unaligned

A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four.

Word

A 32-bit data item.

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