3.1. About the programmer’s model

Table 3.1 lists the PL301 registers.

Table 3.1. PL301 register summary

AddressType Width

Reset

value

NameDescription
0x400[1]R/W320x00000000QoS Tidemark for MI 0See Programmable Quality of Service (ProgQoS)
0x404[2]R/W320x00000000QoS Access Control for MI 0
0x408[3]R/W32ConfiguredAR channel arbitration value for MI 0See Arbitration
0x40C[4]R/W32ConfiguredAW channel arbitration value for MI 0
0x800 - 0xFBC---Reserved-
0xFC0RO320x000000nn[5]PrimeCell Configuration Register 0See Configuration registers
0xFC4RO320x000000nn[6]PrimeCell Configuration Register 1
0xFC8RO320x00000000PrimeCell Configuration Register 2
0xFCCRO320x00000000PrimeCell Configuration Register 3
0xFD0 -0xFDC---Reserved 
0xFE0 RO80x01PrimeCell Peripheral Register 0See PrimeCell Peripheral ID Registers 0-3
0xFE4 RO80x13PrimeCell Peripheral Register 1
0xFE8RO80x14PrimeCell Peripheral Register 2
0xFECRO80x00PrimeCell Peripheral Register 3
0xFF0 RO80x0DPrimeCell ID Register 0See PrimeCell ID Registers 0-3
0xFF4 RO80xF0PrimeCell ID Register 1
0xFF8 RO80x05PrimeCell ID Register 2
0xFFC RO80xB1PrimeCell ID Register 3

[1] Address allocation for QoS Tidemark is 0x400 + 0x20 x n, where n is the number of the relevant MI.

[2] Address allocation for QoS Access Control is 0x404 + 0x20 x n, where n is the number of the relevant MI.

[3] Address allocation for AR channel arbitration control registers is 0x408 + (0x20 x N), where N is the number of the relevant MI.

[4] Address allocation for AW channel arbitration control registers is 0x40C + (0x20 x N), where N is the number of the relevant MI.

[5] Where nn is the number of SIs configured in the range 0x01-0x20.

[6] Where nn is the number of MIs configured in the range 0x01-0x20.

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