2.3. Summary of MI options

Table 2.1 summarizes the standard MI options.

Table 2.1. MI configuration options summary (continued)

OptionDescription
Address range, high memoryUpper bound of the address region of the MI. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Address range, low memoryLower bound of the address region of the MI. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Address range, remap moveDefines the behavior of the address remapping scheme for the MI, activated via the REMAP bus. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Clock domain crossingProvides an appropriate clock domain crossing bridge. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Interface data width

Number of bits for the data bus. This is limited to 32 bits for APB. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.

Interface protocolWhen not set to AXI, instantiates either an AXI to AHB or AXI to APB bridge component as appropriate. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
NameName of the MI and associated top-level ports. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
NumberNumber of the MI. This must be unique and determines the cyclic priority and the layout of the QoS register interface.
Peripheral register slices

Enables you to register the external inputs and outputs of the HPM appropriately for timing closure improvement by placing the required number of register slices between the boundary of the interconnect and the AXI core. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.

Programmable QoSConfigures the HPM to use the programmable QoS scheme. See Programmable Quality of Service (ProgQoS).
Remap range, bitAssigns the bit of the REMAP bus that is used for the remap alias. The least significant bit takes priority if more than one bit is active. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Remap range, high memoryUpper bound of the aliased address region of the MI when the relevant bit of the REMAP bus is HIGH. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Remap range, low memoryLower bound of the aliased address region of the MI when the relevant bit of the REMAP bus is HIGH. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Write interleave capabilityNumber of active write transactions for which the MI is capable of transmitting data. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.
Write issuing capabilityMaximum number of active write transactions that the MI can generate at any one time. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.

Table 2.2 summarizes the MI options you require for each active APB peripheral slot if you configure an APB bridge.

Table 2.2. MI configuration options summary for an APB bridge

OptionDescription
APB interface, slot IDIdentifies the peripheral slot and indicates that it is to be connected to a peripheral.
APB interface, nameThe name of the slot, to be appended to the APB signal names at the HPM top-level.
APB interface, versionConfigures the APB protocol version for the slot. This can be 2.0 or 3.0.
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