3.3.1. Address map

The per-master-interface register space starts at 0x400 and extends to 0x7FC. Each MI that is configured to support QoS filtering contains the registers at the following offsets:

0x0  – QoS Tidemark
0x4  – QoS Access Control

When more than one MI with QoS support is included, the register maps for each interface are stacked at 0x20 intervals. The AMBA Designer MI number configuration option determines the address offset for any particular MI.

It is recommended that you assign low MI numbers to MIs that require QoS support. This approach aligns well with the cyclic priority scheme because MIs that require QoS support are typically those that can be considered high-ranking slaves. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual.

There are two registers for each SI:

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