3.4.2. PrimeCell Peripheral ID Registers 0-3

The periph_id registers are four eight-bit read-only registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value. An external master reads them to determine the HPM version of the device.

Table 3.3 lists the register bit assignments.

Table 3.3. periph_id Register bit assignments

BitsName

Description

[31:24]-Undefined
[23:20]-The peripheral revision number is revision-dependent.
[19:12]designerDesigner’s ID number. This is 0x41 for ARM.
[11:0]

part_number

Identifies the peripheral.

The part number for PL301 is 0x301.

Figure 3.2 shows the correspondence between bits of the periph_id registers and the conceptual 32-bit Peripheral ID Register.

Figure 3.2. periph_id Register bit assignments

The following sections describe the periph_id Registers:

Peripheral Identification Register 0

The periph_id_0 Register is hard-coded and the fields within the register determine the reset value. Table 3.4 lists the register bit assignments.

Table 3.4. periph_id_0 Register bit assignments

BitsName

Description

[31:8]-

Read undefined

[7:0]

part_number_0

These bits read back as 0x01

Peripheral Identification Register 1

The periph_id_1 Register is hard-coded and the fields within the register determine the reset value. Table 3.5 lists the register bit assignments.

Table 3.5. periph_id_1 Register bit assignments

BitsName

Description

[31:8]-

Read undefined

[7:4]

designer_0

These bits read back as 0x1

[3:0]

part_number_1

These bits read back as 0x3

Peripheral Identification Register 2

The periph_id_2 Register is hard-coded and the fields within the register determine the reset value. Table 3.6 lists the register bit assignments.

Table 3.6. periph_id_2 Register bit assignments

BitsName

Description

[31:8]-

Read undefined.

[7:4]

revision

These bits read back as the revision number. This can be between 0 and 15:

  • 0x1 = r1p0

  • 0x2 = r1p1

[3:0]

designer_1

These bits read back as 0x4.

Peripheral Identification Register 3

The periph_id_3 register is hard-coded and the fields within the register determine the reset value. Table 3.7 lists the register bit assignments.

Table 3.7. periph_id_3 Register bit assignments

BitsName

Description

[31:8]-

Read undefined.

[7:4]-Reserved for future use. Read undefined.
[3:0]Reserved Always zero.
Copyright © 2006-2007 ARM Limited. All rights reserved.ARM DDI 0422B
Non-Confidential