PrimeCell® DMA Controller (PL330) Technical Reference Manual 3.3.23. Configuration Register 1

3.3.23. Configuration Register 1

The CR1 Register provides information about the instruction cache configuration. Table 3.5 lists the address base offset, reset value, and access type for this register.

Figure 3.24 shows the register bit assignments.

Figure 3.24. CR1 Registers bit assignments

Table 3.30 lists the register bit assignments.

Table 3.30. CR1 Registers bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined.
[7:4]	num_i-cache_lines	Number of i-cache lines: b0000 = 1 i-cache line b0001 = 2 i-cache lines b0010 = 3 i-cache lines . . . b1111 = 16 i-cache lines.
[3]	-	Reserved, read undefined.
[2:0]	i-cache_len	The length of an i-cache line: b000 - b001 = reserved b010 = 4 bytes b011 = 8 bytes b100 = 16 bytes b101 = 32 bytes b110 - b111 = reserved.

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