PrimeCell ® DMAController (PL330) Technical Reference Manual

Revision:r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the DMAC
1.1.1. Features of the DMAC
1.1.2. Configurable features of the DMAC
1.2. Terminology
2. Functional Overview
2.1. Overview
2.2. DMAC interfaces
2.2.1. APB slave interfaces
2.2.2. AXI master interface
2.2.3. Peripheral request interfaces
2.2.4. Interrupt interface
2.2.5. Reset initialization interface
2.3. Operating states
2.3.1. Stopped
2.3.2. Executing
2.3.3. Cache miss
2.3.4. Updating PC
2.3.5. Waiting for event
2.3.6. At barrier
2.3.7. Waiting for peripheral
2.3.8. Faulting completing
2.3.9. Faulting
2.3.10. Killing
2.3.11. Completing
2.4. Initializing the DMAC
2.4.1. Setting the security state of theDMA manager
2.4.2. Setting the location of the firstinstruction for the DMAC to execute
2.4.3. Setting the security state for theinterrupt outputs
2.4.4. Setting the security state for a peripheralrequest interface
2.5. Using the APB slave interfaces
2.5.1. Issuing instructions to the DMAC usingan APB interface
2.6. Peripheral request interface
2.6.1. Mapping to a DMA channel
2.6.2. Handshake rules
2.6.3. Peripheral length management
2.6.4. DMAC length management
2.6.5. Peripheral request interface timingdiagrams
2.7. Using events and interrupts
2.7.1. Using an event to restart DMA channels
2.7.2. Interrupting a microprocessor
2.8. Aborts
2.8.1. Abort types
2.8.2. Abort sources
2.8.3. Watchdog abort
2.8.4. Abort handling
2.9. Security usage
2.9.1. DMA manager thread is in the Securestate
2.9.2. DMA manager thread is in the Non-securestate
2.9.3. DMA channel thread is in the Secure state
2.9.4. DMA channel thread is in the Non-secure state
2.10. Constraints and limitations of use
2.10.1. DMA channel arbitration
2.10.2. DMA channel prioritization
2.10.3. Instruction cache latency
2.11. Programming restrictions
2.11.1. Fixed unaligned bursts
2.11.2. Endian swap size restrictions
2.11.3. Updating DMA channel control registersduring a DMA cycle
2.11.4. Full MFIFO causes DMAC watchdog toabort a DMA channel
3. Programmers Model
3.1. About the programmers model
3.2. DMAC Register summary
3.3. DMAC Register descriptions
3.3.1. DMA Status Register
3.3.2. DMA Program Counter Register
3.3.3. Interrupt Enable Register
3.3.4. Event Status Register
3.3.5. Interrupt Status Register
3.3.6. Interrupt Clear Register
3.3.7. Fault Status DMA ManagerRegister
3.3.8. Fault Status DMA ChannelRegister
3.3.9. Fault Type DMA ManagerRegister
3.3.10. Fault Type DMA Channel Registers
3.3.11. Channel Status Registers
3.3.12. Channel ProgramCounter Registers
3.3.13. Source Address Registers
3.3.14. Destination AddressRegisters
3.3.15. Channel Control Registers
3.3.16. Loop Counter 0 Registers
3.3.17. Loop Counter 1 Registers
3.3.18. Debug Status Register
3.3.19. Debug Command Register
3.3.20. Debug Instruction-0 Register
3.3.21. Debug Instruction-1 Register
3.3.22. Configuration Register 0
3.3.23. Configuration Register 1
3.3.24. Configuration Register 2
3.3.25. Configuration Register 3
3.3.26. Configuration Register 4
3.3.27. Configuration Register Dn
3.3.28. Peripheral Identification Registers0-3
3.3.29. PrimeCell Identification Registers0-3
4. Instruction Set
4.1. Instruction syntax conventions
4.2. Instruction set summary
4.3. Instructions
4.3.1. DMAADDH
4.3.2. DMAEND
4.3.3. DMAFLUSHP
4.3.4. DMAGO
4.3.5. DMALD[S|B]
4.3.6. DMALDP<S|B>
4.3.7. DMALP
4.3.8. DMALPEND[S|B]
4.3.9. DMALPFE
4.3.10. DMAKILL
4.3.11. DMAMOV
4.3.12. DMANOP
4.3.13. DMARMB
4.3.14. DMASEV
4.3.15. DMAST[S|B]
4.3.16. DMASTP<S|B>
4.3.17. DMASTZ
4.3.18. DMAWFE
4.3.19. DMAWFP<S|B|P>
4.3.20. DMAWMB
4.4. Assembler directives
4.4.1. DCD
4.4.2. DCB
4.4.3. DMALP
4.4.4. DMALPFE
4.4.5. DMALPEND
4.4.6. DMAMOV CCR
A. Signal Descriptions
A.1. Clocks and resets
A.2. AXI signals
A.2.1. Write address (AXI-AW)channel signals
A.2.2. Write data (AXI-W) channel signals
A.2.3. Write response (AXI-B) channel signals
A.2.4. Read address (AXI-AR)channel signals
A.2.5. Read data (AXI-R)channel signals
A.3. APB signals
A.3.1. Non-secure APB interface
A.3.2. Secure APB interface
A.4. Peripheral request interface
A.5. Interrupt signals
A.6. Tie-off signals
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Interfaces on the DMAC
1.2. Example system
2.1. DMAC block diagram
2.2. APB slave interfaces
2.3. AXI master interface connections
2.4. Peripheral request interface
2.5. Interrupt interface
2.6. Reset initialization interface
2.7. Thread operating states
2.8. Request and acknowledge buses onthe peripheral request interface
2.9. Burst request signaling
2.10. Single and burst request signaling
2.11. Single transfers for a burst request
2.12. Abort process
2.13. Equation for the maximum number ofconsecutive DMALD
2.14. DMAC operating with four DMA channels
2.15. Equation for the maximum number ofconsecutive DMAST
3.1. DMAC summary register map
3.2. DS Register bit assignments
3.3. DPC Register bit assignments
3.4. INTEN Register bit assignments
3.5. ES Register bit assignments
3.6. INTSTATUS Register bit assignments
3.7. INTCLR Register bit assignments
3.8. FSM Register bit assignments
3.9. FSC Register bit assignments
3.10. FTM Register bit assignments
3.11. FTC Register bit assignments
3.12. CSn Registerbit assignments and address offsets
3.13. CPCn Registerbit assignments and address offsets
3.14. SA_n Registerbit assignments and address offsets
3.15. DA_n Registerbit assignments and address offsets
3.16. CC_n Registerbit assignments
3.17. LC0_n Registerbit assignments
3.18. LC1_n Registerbit assignments
3.19. DBGSTATUS Register bit assignments
3.20. DBGCMD Register bit assignments
3.21. DBGINST0 Register bit assignments
3.22. DBGINST1 Register bit assignments
3.23. CR0 Register bit assignments
3.24. CR1 Registers bit assignments
3.25. CR2 Registers bit assignments
3.26. CR3 Registers bit assignments
3.27. CR4 Registers bit assignments
3.28. CRDn Register bit assignments
3.29. periph_id Register bit assignments
3.30. pcell_id Register bit assignments
4.1. DMAADDH encoding
4.2. DMAEND encoding
4.3. DMAFLUSHP encoding
4.4. DMAGO encoding
4.5. DMALD[S|B] encoding
4.6. DMALDP<S|B> encoding
4.7. DMALP encoding
4.8. DMALPEND[S|B] encoding
4.9. DMAKILL encoding
4.10. DMAMOV encoding
4.11. DMANOP encoding
4.12. DMARMB encoding
4.13. DMASEV encoding
4.14. DMAST[S|B] encoding
4.15. DMASTP<S|B> encoding
4.16. DMASTZ encoding
4.17. DMAWFE encoding
4.18. DMAWFP<S|B|P> encoding
4.19. DMAWMB encoding

List of Tables

2.1. AXI characteristics for a DMA transfer
2.2. Handshake rules
3.1. DMAC Control Register summary
3.2. DMA channel thread status register summary
3.3. AXI status and loop counter register summary
3.4. DMAC Debug Register summary
3.5. DMAC Configuration Register summary
3.6. Peripheral and PrimeCell Identification Register summary
3.7. DS Register bit assignments
3.8. DPC Register bit assignments
3.9. INTEN Register bit assignments
3.10. ES Register bit assignments
3.11. INTSTATUS Register bit assignments
3.12. INTCLR Register bit assignments
3.13. FSM Register bit assignments
3.14. FSC Register bit assignments
3.15. FTM Register bit assignments
3.16. FTC Register bit assignments
3.17. CSn Register bit assignments
3.18. CPCn Register bit assignments
3.19. SA_n Register bit assignments
3.20. DA_n Register bit assignments
3.21. CC_n Register bit assignments
3.22. Swap data
3.23. LC0_n Register bit assignments
3.24. LC1_n Register bit assignments
3.25. DBGSTATUS Register bit assignments
3.26. DBGCMD Register bit assignments
3.27. DBGINST0 Register bit assignments
3.28. DBGINST1 Register bit assignments
3.29. CR0 Register bit assignments
3.30. CR1 Registers bit assignments
3.31. CR2 Register bit assignments
3.32. CR3 Register bit assignments
3.33. CR4 Register bit assignments
3.34. CRDn Registers bit assignments
3.35. periph_id Register bit assignments
3.36. periph_id_0 Register bit assignments
3.37. periph_id_1 Register bit assignments
3.38. periph_id_2 Register bit assignments
3.39. periph_id_3 Register bit assignments
3.40. pcell_id Register bit assignments
3.41. pcell_id_0 Register bit assignments
3.42. pcell_id_1 Register bit assignments
3.43. pcell_id_2 Register bit assignments
3.44. pcell_id_3 Register bit assignments
4.1. Instruction syntax summary
4.2. DMAMOV CCR argument description and thedefault values
A.1. Clock and reset
A.2. AXI-AW signals
A.3. AXI-W signals
A.4. AXI-B signals
A.5. AXI-AR signals
A.6. AXI-R signals
A.7. Non-secure APB interface signals
A.8. Secure APB interface signals
A.9. Peripheral request interface
A.10. Interrupt signals
A.11. DMAC tie-off signals
A.12. Interrupt and peripheral tie-off signals

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Product Status

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Revision History
Revision A 19December 2007 First issue for the r0p0 release
Copyright © 2007 ARM Limited. All rights reserved. ARM DDI 0424A
Non-Confidential