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Table A.1 shows the clock and reset signals.
Table A.1. Clock and reset
| Name | Type | Source/ destination | Description |
|---|---|---|---|
| aclk | Input | Clock source | AXI clock. |
| aresetn | Input | Reset source | DMAC active-LOW reset: 0 = apply DMAC reset 1 = do not apply DMAC reset. |
pclken | Input | Clock generator | Clock enable signal that enables the APB interfaces to operate at either:
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