A.1. Clocks and resets

Table A.1 shows the clock and reset signals.

Table A.1. Clock and reset

NameType

Source/

destination

Description
aclkInputClock sourceAXI clock.
aresetnInputReset source

DMAC active-LOW reset:

0 = apply DMAC reset

1 = do not apply DMAC reset.

pclken

Input

Clock generator

Clock enable signal that enables the APB interfaces to operate at either:

  • the aclk frequency

  • a divided integer multiple of aclk that is aligned to aclk.

    Note

    If you do not use pclken then you must tie it HIGH. This results in aclk clocking the APB interfaces.


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