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The MFIFO is a shared resource that is utilized on a first-come-first-served basis by all currently active channels. To a program, it appears as a set of variable-depth parallel FIFOs, one per channel, with the restriction that the total depth of all the FIFOs cannot exceed the configured size of the MFIFO. The width of the AXI master interface sets the MFIFO width and the MFIFO depth is configurable.
The DMAC is capable of realigning data from the source to
the destination. For example, the DMAC shifts the data by two byte
lanes when it reads a word from address 0x103 and
writes to address 0x205. All byte manipulations
occur when data enters the MFIFO (as a result of an AXI read due
to a DMALD instruction) so that the DMAC does not need
to manipulate the data when it removes it from the MFIFO (as a result
of an AXI write due to a DMAST instruction). Therefore the
storage and packing of the data in the MFIFO is determined by the
destination address and transfer characteristics.
When a program specifies that incrementing transactions are
to be performed to the destination, the DMAC packs data into the
MFIFO to minimise the usage of the MFIFO entries. For example, a
DMAC with a 64-bit AXI data bus where the program loads two 32-bit
words from address 0x100 and the destination address
is set to 0x200. In this case, the DMAC packs the two words
into a single 64-bit entry in the MFIFO.
In certain situations, the number of entries required to store the data loaded from a source is not a simple calculation of amount of source data divided by MFIFO width. The calculation of the number of entries required is not simple when any of the following occur:
the source address is not aligned to the AXI bus width
the destination address is not aligned to the AXI bus width
the transactions are to a fixed destination, that is, a non-incrementing address.
The DMALD and DMAST instructions
each specify that an AXI transaction is to be performed. The amount
of data transferred by an AXI transaction depends on the values
programmed in to the CCRn Register and
the address of the transaction. See the AMBA AXI Protocol
Specification for information about unaligned transfers.
The following sections provide several example DMAC programs together with illustrations of the MFIFO usage:
These sections show MFIFO usage in the following ways:
a graph of the number of MFIFO entries versus time
a diagram of the byte-lane manipulation that the DMAC performs when data enters the MFIFO.
All the examples use a DMAC configuration with a 64-bit AXI data bus. The numbers 0 and 7 in the MFIFO diagrams indicate the byte lanes in the MFIFO.
| Copyright © 2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0424B |
| Non-Confidential | |
| PDF version | |
| Home > MFIFO Usage Overview > About MFIFO usage overview |