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The CR1 Register characteristics are:
Provides information about the instruction cache configuration.
No usage constraints.
Available in all configurations of the DMAC.
See the register summary in Table 3.5.
Figure 3.24 shows the CR1 Register bit assignments.
Table 3.30 shows the CR1 Register bit assignments.
Table 3.30. CR1 Registers bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Reserved, read undefined. |
| [7:4] | num_i-cache_lines | Number of i-cache lines: b0000 = 1 i-cache line b0001 = 2 i-cache lines b0010 = 3 i-cache lines . . . b1111 = 16 i-cache lines. |
| [3] | - | Reserved, read undefined. |
| [2:0] | i-cache_len | The length of an i-cache line: b000 - b001 = reserved b010 = 4 bytes b011 = 8 bytes b100 = 16 bytes b101 = 32 bytes b110 - b111 = reserved. |
| Copyright © 2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0424B |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Register descriptions > Configuration Register 1 |