AMBA DMA Controller DMA-330 Technical Reference ManualRevision: r1p0
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3.3.6. Interrupt Clear Register

The INTCLR Register characteristics are:

Purpose

Provides the status of the active interrupts in the DMAC.

Usage constraints

No usage constraints.

Configurations

Available in all configurations of the DMAC.

Attributes

See the register summary in Table 3.1.

Figure 3.7 shows the INTCLR Register bit assignments.

Figure 3.7. INTCLR Register bit assignments


Table 3.12 shows the INTCLR Register bit assignments.

Table 3.12. INTCLR Register bit assignments

Bits

Name

Function

[31:0]irq_clr

Controls the clearing of the irq outputs:

Bit [N] = 0

The status of irq[N] does not change.

Bit [N] = 1

The DMAC sets irq[N] LOW if the INTEN Register programs the DMAC to signal an interrupt. Otherwise, the status of irq[N] does not change. See Interrupt Enable Register.


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