AMBA DMA Controller DMA-330 Technical Reference ManualRevision: r1p0
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3.3.1. DMA Manager Status Register

The DSR Register characteristics are:

Purpose

Returns information about the status of the DMA manager thread.

Usage constraints

No usage constraints.

Configurations

Available in all configurations of the DMAC.

Attributes

See the register summary in Table 3.1.

Figure 3.2 shows the DSR Register bit assignments.

Figure 3.2. DSR Register bit assignments


Table 3.7 shows the DSR Register bit assignments.

Table 3.7. DSR Register bit assignments

Bits

Name

Function

[31:10]

-

Read undefined.

[9]DNS

Provides the security status of the DMA manager thread:

0 = DMA manager operates in the Secure state

1 = DMA manager operates in the Non-secure state.

Note

You must use the boot_manager_ns signal to set the secure state of the DMA manager thread.

[8:4]Wakeup_event

When the DMA manager thread executes a DMAWFE instruction, it waits for the following event to occur:

b00000 = event[0]

b00001 = event[1]

b00010 = event[2]

.

.

.

b11111 = event[31].

[3:0]DMA status

The operating state of the DMA manager:

b0000 = Stopped

b0001 = Executing

b0010 = Cache miss

b0011 = Updating PC

b0100 = Waiting for event

b0101-b1110 = reserved

b1111 = Faulting.

See Operating states for more information.


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