AMBA DMA Controller DMA-330 Technical Reference Manual: 3.2. Register summary

3.2. Register summary

The following tables show the DMAC registers in base offset order:

Table 3.1 shows the control registers and provides information about their address offsets, access permissions when using the secure and non-secure APB interfaces, and a brief description.

Table 3.1. DMAC control register summary

Offset	Name	Secure RW	Non-secure RW when:		Reset	Description
Offset	Name	Secure RW	thread is secure ^[a]	thread is non-secure ^[a]	Reset	Description
`0x000`	DSR	RO	Read As Zero (RAZ)	RO	`0x0`	DMA Manager Status Register
`0x004`	DPC	RO	RAZ	RO	`0x0`	DMA Program Counter Register
`0x008` - `0x01C`	-	-	-	-	`-`	Reserved
`0x020`	INTEN	RW	RAZ	RW	`0x0`	Interrupt Enable Register
`0x024`	INT_EVENT_RIS	RO	RAZ	RO	`0x0`	Event-Interrupt Raw Status Register
`0x028`	INTMIS	RO	RAZ	RO	`0x0`	Interrupt Status Register
`0x02C`	INTCLR	WO	RAZ	WO	`0x0`	Interrupt Clear Register
`0x030`	FSRD	RO	RAZ	RO	`0x0`	Fault Status DMA Manager Register
`0x034`	FSRC	RO	RAZ	RO	`0x0`	Fault Status DMA Channel Register
`0x038`	FTRD	RO	RAZ	RO	`0x0`	Fault Type DMA Manager Register
`0x03C`	-	-	-	-	`-`	Reserved
Fault Type DMA Channel Registers
`0x040` `0x044` `0x048` `0x04C` `0x050` `0x054` `0x058` `0x05C`	FTR0 FTR1 FTR2 FTR3 FTR4 FTR5 FTR6 FTR7	RO	RAZ	RO	`0x0`	Fault type for DMA channel 0 Fault type for DMA channel 1 Fault type for DMA channel 2 Fault type for DMA channel 3 Fault type for DMA channel 4 Fault type for DMA channel 5 Fault type for DMA channel 6 Fault type for DMA channel 7
`0x060` - `0x0FC`	-	-	-	-	`-`	Reserved
^[a]You must use the boot_manager_ns signal to set the security state for the DMA manager thread. See the DMA Manager Status Register for information about the security state of the DMA manager thread.

Table 3.2 shows the DMA channel thread status registers and provides information about their address offsets, access permissions when using the secure and non-secure APB interfaces, and a brief description.

Table 3.2. DMA channel thread status register summary

Offset	Name	Secure RW	Non-secure RW when:		Reset	Description
Offset	Name	Secure RW	channel is secure ^[a]	channel is non-secure ^[a]	Reset	Description
Channel Status Registers
`0x100` `0x108` `0x110` `0x118` `0x120` `0x128` `0x130` `0x138`	CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7	RO	RAZ	RO	`0x0`	Channel status for DMA channel 0 Channel status for DMA channel 1 Channel status for DMA channel 2 Channel status for DMA channel 3 Channel status for DMA channel 4 Channel status for DMA channel 5 Channel status for DMA channel 6 Channel status for DMA channel 7
Channel Program Counter Registers
`0x104` `0x10C` `0x114` `0x11C` `0x124` `0x12C` `0x134` `0x13C`	CPC0 CPC1 CPC2 CPC3 CPC4 CPC5 CPC6 CPC7	RO	RAZ	RO	`0x0`	Channel PC for DMA channel 0 Channel PC for DMA channel 1 Channel PC for DMA channel 2 Channel PC for DMA channel 3 Channel PC for DMA channel 4 Channel PC for DMA channel 5 Channel PC for DMA channel 6 Channel PC for DMA channel 7
`0x140` - `0x3FC`	-	-	-	-	`-`	Reserved
^[a]The security state for the channel is set by the security of the `DMAGO` instruction and the security state of the DMA manager thread. See the relevant Channel Status Registers for information about the security state of the channel.

Table 3.3 shows the AXI status and loop counter registers and provides information about their address offsets, access permissions when using the secure and non-secure APB interfaces, and a brief description.

Table 3.3. AXI status and loop counter register summary

	Offset	Name	Secure RW	Non-secure RW when:		Reset	Description
	Offset	Name	Secure RW	channel is secure ^[a]	channel is non-secure ^[a]	Reset	Description
	Source Address Registers
	`0x400` `0x420` `0x440` `0x460` `0x480` `0x4A0` `0x4C0` `0x4E0`	SAR0 SAR1 SAR2 SAR3 SAR4 SAR5 SAR6 SAR7	RO	RAZ	RO	`0x0`	Source address for DMA channel 0 Source address for DMA channel 1 Source address for DMA channel 2 Source address for DMA channel 3 Source address for DMA channel 4 Source address for DMA channel 5 Source address for DMA channel 6 Source address for DMA channel 7
	Destination Address Registers
	`0x404` `0x424` `0x444` `0x464` `0x484` `0x4A4` `0x4C4` `0x4E4`	DAR0 DAR1 DAR2 DAR3 DAR4 DAR5 DAR6 DAR7	RO	RAZ	RO	`0x0`	Destination address for DMA channel 0 Destination address for DMA channel 1 Destination address for DMA channel 2 Destination address for DMA channel 3 Destination address for DMA channel 4 Destination address for DMA channel 5 Destination address for DMA channel 6 Destination address for DMA channel 7
	Channel Control Registers
	`0x408` `0x428` `0x448` `0x468` `0x488` `0x4A8` `0x4C8` `0x4E8`	CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCR7	RO	RAZ	RO	`0x0`	Channel control for DMA channel 0 Channel control for DMA channel 1 Channel control for DMA channel 2 Channel control for DMA channel 3 Channel control for DMA channel 4 Channel control for DMA channel 5 Channel control for DMA channel 6 Channel control for DMA channel 7
	Loop Counter 0 Registers
	`0x40C` `0x42C` `0x44C` `0x46C` `0x48C` `0x4AC` `0x4CC` `0x4EC`	LC0_0 LC0_1 LC0_2 LC0_3 LC0_4 LC0_5 LC0_6 LC0_7	RO	RAZ	RO	`0x0`	Loop counter 0 for DMA channel 0 Loop counter 0 for DMA channel 1 Loop counter 0 for DMA channel 2 Loop counter 0 for DMA channel 3 Loop counter 0 for DMA channel 4 Loop counter 0 for DMA channel 5 Loop counter 0 for DMA channel 6 Loop counter 0 for DMA channel 7
	Loop Counter 1 Registers
	`0x410` `0x430` `0x450` `0x470` `0x490` `0x4B0` `0x4D0` `0x4F0`	LC1_0 LC1_1 LC1_2 LC1_3 LC1_4 LC1_5 LC1_6 LC1_7	RO	RAZ	RO	`0x0`	Loop counter 1 for DMA channel 0 Loop counter 1 for DMA channel 1 Loop counter 1 for DMA channel 2 Loop counter 1 for DMA channel 3 Loop counter 1 for DMA channel 4 Loop counter 1 for DMA channel 5 Loop counter 1 for DMA channel 6 Loop counter 1 for DMA channel 7
	`0x414` - `0x41C`	-	-	-	-	`-`	Reserved
	`0x434` - `0x43C`	-	-	-	-	`-`	Reserved
	`0x454` - `0x45C`	-	-	-	-	`-`	Reserved
	`0x474` - `0x47C`	-	-	-	-	`-`	Reserved
	`0x494` - `0x49C`	-	-	-	-	`-`	Reserved
	`0x4B4` - `0x4BC`	-	-	-	-	`-`	Reserved
	`0x4D4` - `0x4DC`	-	-	-	-	`-`	Reserved
	`0x4F4` - `0xCFC`	-	-	-	-	`-`	Reserved
^[a]The security state for the channel is set by the security of the `DMAGO` instruction and the security state of the DMA manager thread. See the relevant Channel Status Registers for information about the security state of the channel.

Table 3.4 shows the debug registers and provides information about their address offsets, access permissions when using the secure and non-secure APB interfaces, and a brief description.

Table 3.4. DMAC debug register summary

Offset	Name	Secure RW	Non-secure RW when:		Reset	Description
Offset	Name	Secure RW	thread is secure ^[a]	thread is non-secure ^[a]	Reset	Description
`0xD00`	DBGSTATUS	RO	RAZ	RO	`0x0`	Debug Status Register
`0xD04`	DBGCMD	WO	RAZ	WO	-	Debug Command Register
`0xD08`	DBGINST0	WO	RAZ	WO	-	Debug Instruction-0 Register
`0xD0C`	DBGINST1	WO	RAZ	WO	-	Debug Instruction-1 Register
`0xD10` -`0xDFC`	-	-	-	-	`-`	Reserved
^[a]You must use the boot_manager_ns signal to set the security state for the DMA manager thread. See the DMA Manager Status Register for information about the security state of the DMA manager thread.

Table 3.5 shows the configuration registers and provides information about their address offsets, access permissions when using the secure and non-secure APB interfaces, and a brief description.

Table 3.5. DMAC configuration register summary

Offset	Name	Secure RW	Non-secure RW when:		Reset	Description
Offset	Name	Secure RW	thread is secure ^[a]	thread is non-secure ^[a]	Reset	Description
`0xE00`	CR0	RO	RAZ	RO	- ^[b]	Configuration Register 0
`0xE04`	CR1	RO	RAZ	RO	- ^[b]	Configuration Register 1
`0xE08`	CR2	RO	RAZ	RO	- ^[b]	Configuration Register 2
`0xE0C`	CR3	RO	RAZ	RO	- ^[b]	Configuration Register 3
`0xE10`	CR4	RO	RAZ	RO	- ^[b]	Configuration Register 4
`0xE14`	CRD	RO	RAZ	RO	- ^[b]	DMA Configuration Register
`0xE18` -`0xE7C`	-	-	-	-	`-`	Reserved
`0xE80`	WD	RW	RAZ	RW	`-`	Watchdog Register
`0xE84` -`0xFDC`	-	-	-	-	`-`	Reserved
^[a]You must use the boot_manager_ns signal to set the security state for the DMA manager thread. See the DMA Manager Status Register for information about the security state of the DMA manager thread. ^[b]Configuration-dependent.

Table 3.6 shows the Peripheral Identification Registers and Component Identification Registers.

Table 3.6. Peripheral and component identification register summary

Offset	Name	Type	Reset	Description
`0xFE0` - `0xFEC`	periph_id_n	RO	Configuration-dependent	Peripheral Identification Registers
`0xFF0` - `0xFFC`	pcell_id_n	RO	Configuration-dependent	Component Identification Registers 0-3

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