CoreLink DMA Controller DMA-330 Technical Reference ManualRevision: r1p1
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3.3.23. Configuration Register 1

The CR1 Register characteristics are:

Purpose

Provides information about the instruction cache configuration.

Usage constraints

No usage constraints.

Configurations

Available in all configurations of the DMAC.

Attributes

See the register summary in Table 3.5.

Figure 3.24 shows the CR1 Register bit assignments.

Figure 3.24. CR1 Register bit assignments

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Table 3.30 shows the CR1 Register bit assignments.

Table 3.30. CR1 Registers bit assignments

BitsNameFunction
[31:8]-Reserved, read undefined.
[7:4]num_i-cache_lines

Number of i-cache lines:

b0000 = 1 i-cache line

b0001 = 2 i-cache lines

b0010 = 3 i-cache lines

.

.

.

b1111 = 16 i-cache lines.

[3]-Reserved, read undefined.
[2:0]i-cache_len

The length of an i-cache line:

b000 - b001 = reserved

b010 = 4 bytes

b011 = 8 bytes

b100 = 16 bytes

b101 = 32 bytes

b110 - b111 = reserved.


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