CoreLink DMA Controller DMA-330 Technical Reference Manual: 3.3.29. Peripheral Identification Registers

3.3.29. Peripheral Identification Registers

The periph_id_[3:0] Register characteristics are:

Purpose: Provides information about the configuration and version of the peripheral.
Usage constraints: No usage constraints.
Configurations: Available in all configurations of the DMAC.
Attributes: See the register summary in Table 3.6.

These registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value. Figure 3.30 shows the correspondence between bits [7:0] of the periph_id registers and the conceptual 32-bit Peripheral ID Register.

Figure 3.30. periph_id Register bit assignments

Table 3.36 shows the bit assignments for the conceptual 32-bit peripheral ID register.

Table 3.36. Conceptual peripheral ID register bit assignments

Bits	Name	Description
[31:25]	-	Reserved, read undefined.
[24]	integration_cfg	Identifies if the DMAC contains integration test logic. See Table 3.40.
[23:20]	revision	Identifies the RTL revision of the peripheral. See Table 3.39.
[19:12]	designer	Identifies the designer. This is `0x41` for ARM.
[11:0]	part_number	Identifies the peripheral. The part number for the DMAC is `0x330`.

The following subsections describe the periph_id registers:

Peripheral Identification Register 0

The periph_id_0 Register is hard-coded and the fields in the register control the reset value. Table 3.37 shows the bit assignments.

Table 3.37. periph_id_0 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:0]	part_number_0	Returns `0x30`

Peripheral Identification Register 1

The periph_id_1 Register is hard-coded and the fields in the register control the reset value. Table 3.38 shows the bit assignments.

Table 3.38. periph_id_1 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:4]	designer_0	Returns `0x1`
[3:0]	part_number_1	Returns `0x3`

Peripheral Identification Register 2

The periph_id_2 Register is hard-coded and the fields in the register control the reset value. Table 3.39 shows the bit assignments.

Table 3.39. periph_id_2 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined.
[7:4]	revision	Identifies the revision: `0x0` for r0p0 `0x1` for r1p0 `0x2` for r1p1.
[3:0]	designer_1	Returns `0x4`.

Peripheral Identification Register 3

The periph_id_3 Register is hard-coded and the fields in the register control the reset value. Table 3.40 shows the bit assignments.

Table 3.40. periph_id_3 Register bit assignments

Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:1]	-	Reserved for future use, read undefined
[0]	integration_cfg	Returns 0 to indicate that the DMAC does not contain integration test logic

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