In this program the source address and destination address are aligned with the AXI data bus width, and the destination address is fixed.

DMAMOV CCR, SB2 SS64 DB4 DS32 DAF

DMAMOV SAR, 0x1000

DMAMOV DAR, 0x4000

DMALP 16

    DMALD    ; shown as a in Figure B.8

    DMAST    ; shown as b in Figure B.8

DMALPEND

DMAEND

Figure B.8 shows the MFIFO usage for this program.

Each DMALD in the program loads two 64-bit data transfers into the MFIFO. Because the destination address is a 32-bit fixed address then the DMAC splits each 64-bit data item across two entries in the MFIFO.

This example has a static requirement of zero MFIFO entries and a dynamic requirement of four MFIFO entries.