CoreLink™ DMA-330 DMA Controller Technical Reference Manual

Revision: r1p2

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the DMAC
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.7.3. ARM architecture and protocol information
1.8. Product revisions
1.9. Terminology
2. Functional Overview
2.1. Overview
2.2. DMAC interfaces
2.2.1. APB slave interfaces
2.2.2. AXI master interface
2.2.3. Peripheral request interfaces
2.2.4. Interrupt interface
2.2.5. Reset initialization interface
2.3. Operating states
2.3.1. Stopped
2.3.2. Executing
2.3.3. Cache miss
2.3.4. Updating PC
2.3.5. Waiting for event
2.3.6. At barrier
2.3.7. Waiting for peripheral
2.3.8. Faulting completing
2.3.9. Faulting
2.3.10. Killing
2.3.11. Completing
2.4. Initializing the DMAC
2.4.1. How to set the security state of the DMA manager
2.4.2. How to set the location of the first instruction for the DMAC to execute
2.4.3. How to set the security state for the interrupt outputs
2.4.4. How to set the security state for a peripheral request interface
2.5. Using the APB slave interfaces
2.5.1. Issuing instructions to the DMAC using an APB interface
2.6. Peripheral request interface
2.6.1. Mapping to a DMA channel
2.6.2. Handshake rules
2.6.3. Request acceptance capability configuration
2.6.4. Peripheral length management
2.6.5. DMAC length management
2.6.6. Peripheral request interface timing diagrams
2.7. Using events and interrupts
2.7.1. Using an event to restart DMA channels
2.7.2. Interrupting a microprocessor
2.8. Aborts
2.8.1. Abort types
2.8.2. Abort sources
2.8.3. Watchdog abort
2.8.4. Abort handling
2.9. Security usage
2.9.1. DMA manager thread is in the Secure state
2.9.2. DMA manager thread is in the Non-secure state
2.9.3. DMA channel thread is in the Secure state
2.9.4. DMA channel thread is in the Non-secure state
2.10. Constraints and limitations of use
2.10.1. DMA channel arbitration
2.10.2. DMA channel prioritization
2.10.3. Instruction cache latency
2.10.4. AXI data transfer size
2.10.5. AXI bursts crossing 4Kbyte boundaries
2.10.6. AXI burst types
2.10.7. AXI write addresses
2.10.8. AXI write data interleaving
2.11. Programming restrictions
2.11.1. Fixed unaligned bursts
2.11.2. Endian swap size restrictions
2.11.3. Updating DMA channel control registers during a DMA cycle
2.11.4. Resource sharing between DMA channels
3. Programmers Model
3.1. About this programmers model
3.1.1. Register map
3.2. Register summary
3.3. Register descriptions
3.3.1. DMA Manager Status Register
3.3.2. DMA Program Counter Register
3.3.3. Interrupt Enable Register
3.3.4. Event-Interrupt Raw Status Register
3.3.5. Interrupt Status Register
3.3.6. Interrupt Clear Register
3.3.7. Fault Status DMA Manager Register
3.3.8. Fault Status DMA Channel Register
3.3.9. Fault Type DMA Manager Register
3.3.10. Fault Type DMA Channel Registers
3.3.11. Channel Status Registers
3.3.12. Channel Program Counter Registers
3.3.13. Source Address Registers
3.3.14. Destination Address Registers
3.3.15. Channel Control Registers
3.3.16. Loop Counter 0 Registers
3.3.17. Loop Counter 1 Registers
3.3.18. Debug Status Register
3.3.19. Debug Command Register
3.3.20. Debug Instruction-0 Register
3.3.21. Debug Instruction-1 Register
3.3.22. Configuration Register 0
3.3.23. Configuration Register 1
3.3.24. Configuration Register 2
3.3.25. Configuration Register 3
3.3.26. Configuration Register 4
3.3.27. DMA Configuration Register
3.3.28. Watchdog Register
3.3.29. Peripheral Identification Registers
3.3.30. Component Identification Registers 0-3
4. Instruction Set
4.1. Instruction syntax conventions
4.2. Instruction set summary
4.3. Instructions
4.3.1. DMAADDH
4.3.2. DMAADNH
4.3.3. DMAEND
4.3.5. DMAGO
4.3.6. DMAKILL
4.3.7. DMALD[S|B]
4.3.8. DMALDP<S|B>
4.3.9. DMALP
4.3.10. DMALPEND[S|B]
4.3.11. DMALPFE
4.3.12. DMAMOV
4.3.13. DMANOP
4.3.14. DMARMB
4.3.15. DMASEV
4.3.16. DMAST[S|B]
4.3.17. DMASTP<S|B>
4.3.18. DMASTZ
4.3.19. DMAWFE
4.3.20. DMAWFP
4.3.21. DMAWMB
4.4. Assembler directives
4.4.1. DCD
4.4.2. DCB
4.4.3. DMALP
4.4.4. DMALPFE
A. Signal Descriptions
A.1. Clocks and resets
A.2. AXI signals
A.2.1. Write address, AXI-AW, channel signals
A.2.2. Write data, AXI-W, channel signals
A.2.3. Write response, AXI-B, channel signals
A.2.4. Read address, AXI-AR, channel signals
A.2.5. Read data, AXI-R, channel signals
A.3. APB signals
A.3.1. Non-secure APB interface
A.3.2. Secure APB interface
A.4. Peripheral request interface
A.5. Interrupt signals
A.6. Tie-off signals
B. MFIFO Usage Overview
B.1. About MFIFO usage overview
B.2. Aligned transfers
B.2.1. Simple aligned program
B.2.2. Aligned asymmetric program with multiple loads
B.2.3. Aligned asymmetric program with multiple stores
B.3. Unaligned transfers
B.3.1. Aligned source address to unaligned destination address
B.3.2. Unaligned source address to aligned destination address
B.3.3. Unaligned source address to aligned destination address, with excess initial load
B.3.4. Aligned burst size, unaligned MFIFO
B.4. Fixed transfers
B.4.1. Fixed destination with aligned address
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Interfaces on the DMAC
1.2. Example system
2.1. DMAC block diagram
2.2. APB slave interfaces
2.3. AXI master interface connections
2.4. Peripheral request interface
2.5. Interrupt interface
2.6. Reset initialization interface
2.7. Thread operating states
2.8. Request and acknowledge buses on the peripheral request interface
2.9. Burst request signaling
2.10. Single and burst request signaling
2.11. Single transfers for a burst request
2.12. Abort process
3.1. DMAC summary register map
3.2. DSR Register bit assignments
3.3. DPC Register bit assignments
3.4. INTEN Register bit assignments
3.5. INT_EVENT_RIS Register bit assignments
3.6. INTMIS Register bit assignments
3.7. INTCLR Register bit assignments
3.8. FSRD Register bit assignments
3.9. FSRC Register bit assignments
3.10. FTRD Register bit assignments
3.11. FTRn Register bit assignments
3.12. CSRn Register bit assignments
3.13. CPC Register bit assignments and address offsets
3.14. SARn Register bit assignments and address offsets
3.15. DARn Register bit assignments and address offsets
3.16. CCRn Register bit assignments and base address offsets
3.17. LC0_n Register bit assignments and base address offsets
3.18. LC1_n Register bit assignments and base address offsets
3.19. DBGSTATUS Register bit assignments
3.20. DBGCMD Register bit assignments
3.21. DBGINST0 Register bit assignments
3.22. DBGINST1 Register bit assignments
3.23. CR0 Register bit assignments
3.24. CR1 Register bit assignments
3.25. CR2 Register bit assignments
3.26. CR3 Register bit assignments
3.27. CR4 Register bit assignments
3.28. CRD Register bit assignments
3.29. WD Register bit assignments
3.30. periph_id Register bit assignments
3.31. pcell_id Register bit assignments
4.1. DMAADDH encoding
4.2. DMAADNH encoding
4.3. DMAEND encoding
4.4. DMAFLUSHP encoding
4.5. DMAGO encoding
4.6. DMAKILL encoding
4.7. DMALD[S|B] encoding
4.8. DMALDP<S|B> encoding
4.9. DMALP encoding
4.10. DMALPEND[S|B] encoding
4.11. DMAMOV encoding
4.12. DMANOP encoding
4.13. DMARMB encoding
4.14. DMASEV encoding
4.15. DMAST[S|B] encoding
4.16. DMASTP<S|B> encoding
4.17. DMASTZ encoding
4.18. DMAWFE encoding
4.19. DMAWFP encoding
4.20. DMAWMB encoding
B.1. Simple aligned program
B.2. Aligned asymmetric program with multiple loads
B.3. Aligned asymmetric program with multiple stores
B.4. Aligned to unaligned program
B.5. Unaligned to aligned program
B.6. Unaligned to aligned with excess initial load
B.7. Aligned burst with unaligned MFIFO width
B.8. Fixed destination with aligned address

List of Tables

2.1. AXI characteristics for a DMA transfer
2.2. Handshake rules
3.1. DMAC control register summary
3.2. DMA channel thread status register summary
3.3. AXI status and loop counter register summary
3.4. DMAC debug register summary
3.5. DMAC configuration register summary
3.6. Peripheral and component identification register summary
3.7. DSR Register bit assignments
3.8. DPC Register bit assignments
3.9. INTEN Register bit assignments
3.10. INT_EVENT_RIS Register bit assignments
3.11. INTMIS Register bit assignments
3.12. INTCLR Register bit assignments
3.13. FSRD Register bit assignments
3.14. FSRC Register bit assignments
3.15. FTRD Register bit assignments
3.16. FTRn Register bit assignments
3.17. CSRn Register bit assignments
3.18. CPCn Register bit assignments
3.19. SARn Register bit assignments
3.20. DARn Register bit assignments
3.21. CCRn Register bit assignments
3.22. Swap data
3.23. LC0_n Register bit assignments
3.24. LC1_n Register bit assignments
3.25. DBGSTATUS Register bit assignments
3.26. DBGCMD Register bit assignments
3.27. DBGINST0 Register bit assignments
3.28. DBGINST1 Register bit assignments
3.29. CR0 Register bit assignments
3.30. CR1 Registers bit assignments
3.31. CR2 Register bit assignments
3.32. CR3 Register bit assignments
3.33. CR4 Register bit assignments
3.34. CRD Registers bit assignments
3.35. WD Register bit assignments
3.36. Conceptual peripheral ID register bit assignments
3.37. periph_id_0 Register bit assignments
3.38. periph_id_1 Register bit assignments
3.39. periph_id_2 Register bit assignments
3.40. periph_id_3 Register bit assignments
3.41. pcell_id Register bit assignments
4.1. Instruction syntax summary
4.2. DMAMOV CCR argument description and the default values
A.1. Clock and reset
A.2. AXI-AW signals
A.3. AXI-W signals
A.4. AXI-B signals
A.5. AXI-AR signals
A.6. AXI-R signals
A.7. Non-secure APB interface signals
A.8. Secure APB interface signals
A.9. Peripheral request interface
A.10. Interrupt signals
A.11. DMAC tie-off signals
A.12. Interrupt and peripheral tie-off signals
C.1. Differences between issue A and issue B
C.2. Differences between issue B and issue C
C.3. Differences between issue C and issue D

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A19 December 2007First issue for r0p0
Revision B19 November 2009First issue for r1p0
Revision C22 July 2010First issue for r1p1
Revision D29 June 2012First issue for r1p2.
Copyright © 2007, 2009-2010, 2012 ARM. All rights reserved.ARM DDI 0424D