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The following sections describe the AXI master interface signals:
Table A.7 lists the AXI write address signals for the AXI master interface.
Table A.7. AXI-AW signals for the AXI master interface
| Signal | AMBA equivalent [a] |
|---|---|
| awaddrm[AXI_ADDRESS_MSB:0] [b] | AWADDR[31:0] |
| awburstm[1:0] | AWBURST[1:0] |
| awcachem[3:0] | AWCACHE[3:0] |
| awidm[AID_WIDTH -1:0] [b] | AWID[3:0] |
| awlenm[3:0] | AWLEN[3:0] |
| awlockm[1:0] | AWLOCK[1:0] |
| awprotm[2:0] | AWPROT[2:0] |
| awreadym | AWREADY |
| awsizem[2:0] | AWSIZE[2:0] |
| awuserm[AWUSER_WIDTH-1:0] [b] [c] | - |
| awvalidm | AWVALID |
[a] See the AMBA AXI Protocol v1.0 Specification for a description of these signals. [b] The bus width is set when you configure the TZASC. [c] The use of this sideband signal is user-defined. | |
Table A.8 lists the AXI write data signals for the AXI master interface.
Table A.8. AXI-W signals for the AXI master interface
| Signal | AMBA equivalent [a] |
|---|---|
| wdatam[AXI_DATA_MSB:0] [b] | WDATA[31:0] |
| widm[AID_WIDTH-1:0] [b] | WID[3:0] |
| wlastm | WLAST |
| wreadym | WREADY |
| wstrbm[AXI_STRB_MSB:0] [b] | WSTRB[3:0] |
| wuserm[WUSER_WIDTH-1:0] [b] [c] | - |
| wvalidm | WVALID |
[a] See the AMBA AXI Protocol v1.0 Specification for a description of these signals. [b] The bus width is set when you configure the TZASC. [c] The use of this sideband signal is user-defined. | |
Table A.9 lists the AXI write response signals for the AXI master interface.
Table A.9. AXI-B signals for the AXI master interface
| Signal | AMBA equivalent [a] |
|---|---|
| bidm[AID_WIDTH- 1:0] [b] | BID[3:0] |
| breadym | BREADY |
| brespm[1:0] | BRESP[1:0] |
| buserm[BUSER_WIDTH-1:0] [b] [c] | - |
| bvalidm | BVALID |
[a] See the AMBA AXI Protocol v1.0 Specification for a description of these signals. [b] The bus width is set when you configure the TZASC. [c] The use of this sideband signal is user-defined. | |
Table A.10 lists the AXI read address signals for the AXI master interface.
Table A.10. AXI-AR signals for the AXI master interface
| Signal | AMBA equivalent [a] |
|---|---|
| araddrm[AXI_ADDRESS_MSB:0] [b] | ARADDR[31:0] |
| arburstm[1:0] | ARBURST[1:0] |
| arcachem[3:0] | ARCACHE[3:0] |
| aridm[AID_WIDTH - 1:0] | ARID[3:0] |
| arlenm[3:0] | ARLEN[3:0] |
| arlockm[1:0] | ARLOCK[1:0] |
| arprotm[2:0] | ARPROT[2:0] |
| arreadym | ARREADY |
| arsizem[2:0] | ARSIZE[2:0] |
| aruserm[ARUSER_WIDTH-1:0] [b] [c] | - |
| arvalidm | ARVALID |
[a] See the AMBA AXI Protocol v1.0 Specification for a description of these signals. [b] The bus width is set when you configure the TZASC. [c] The use of this sideband signal is user-defined. | |
Table A.11 lists the AXI read data signals for the AXI master interface.
Table A.11. AXI-R signals for the AXI master interface
| Signal | AMBA equivalent [a] |
|---|---|
| rdatam[AXI_DATA_MSB:0] [b] | RDATA[31:0] |
| ridm[AID_WIDTH - 1:0] [b] | RID[3:0] |
| rlastm | RLAST |
| rreadym | RREADY |
| rrespm[1:0] | RRESP[3:0] |
| ruserm[RUSER_WIDTH-1:0] [b] [c] | - |
| rvalidm | RVALID |
[a] See the AMBA AXI Protocol v1.0 Specification for a description of these signals. [b] The bus width is set when you configure the TZASC. [c] The use of this sideband signal is user-defined. | |
| Copyright © 2008, 2010 ARM Limited. All rights reserved. | ARM DDI 0431B |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > AXI signals > AXI master interface signals |