3.2.15. Region Attributes <n> Register

The region_attributes_<n> Register characteristics are:


Controls the permissions for region 0. For all other regions it controls the permissions, region size, subregion disable, and region enable.

Usage constraints

There are no usage constraints.


Available in all configurations of the TZASC.


See the register summary in Table 3.1.

Figure 3.15 shows the region_attributes_<n> Register bit assignments.

Figure 3.15. region_attributes_<n> Register bit assignments

Table 3.15 shows the region_attributes_<n> Register bit assignments.

Table 3.15. region_attributes_<n> Register bit assignments


Permissions setting for region <n>. If an AXI transaction occurs to region n, the value in the sp<n> field controls whether the TZASC permits the transaction to proceed. For more information, see:

[27:16]-Reserved, SBZ.
[15:8]subregion_disable<n> [a]

Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to be disabled:

Bit [15] = 1

Subregion 7 is disabled.

Bit [14] = 1

Subregion 6 is disabled.

Bit [13] = 1

Subregion 5 is disabled.

Bit [12] = 1

Subregion 4 is disabled.

Bit [11] = 1

Subregion 3 is disabled.

Bit [10] = 1

Subregion 2 is disabled.

Bit [9] = 1

Subregion 1 is disabled.

Bit [8] = 1

Subregion 0 is disabled.

For more information, see Subregions and Subregion disable.

[7]-Reserved, SBZ.
[6:1]size<n> [a]

Size of region <n>. See Table 3.16.


The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of this field.

[0]en<n> [a]

Enable for region <n>:

0 = region <n> is disabled

1 = region <n> is enabled.

[a] For region 0, this field is reserved.

Table 3.16 shows how the size<n> field controls the region size and what constraints, if any, the TZASC applies to the base address to ensure that a region starts on the boundary of the region size.

Table 3.16. Region size

size<n> fieldSize of region <n>Base address [a] constraints
b00111164KBBit [15] must be zero
b010000128KBBits [16:15] must be zero
b010001256KBBits [17:15] must be zero
b010010512KBBits [18:15] must be zero
b0100111MBBits [19:15] must be zero
b0101002MBBits [20:15] must be zero
b0101014MBBits [21:15] must be zero
b0101108MBBits [22:15] must be zero
b01011116MBBits [23:15] must be zero
b01100032MBBits [24:15] must be zero
b01100164MBBits [25:15] must be zero
b011010128MBBits [26:15] must be zero
b011011256MBBits [27:15] must be zero
b011100512MBBits [28:15] must be zero
b0111011GBBits [29:15] must be zero
b0111102GBBits [30:15] must be zero
b0111114GBBits [31:15] must be zero
b1000008GBBits [32:15] must be zero
b10000116GBBits [33:15] must be zero
b10001032GBBits [34:15] must be zero
b10001164GBBits [35:15] must be zero
b100100128GBBits [36:15] must be zero
b100101256GBBits [37:15] must be zero
b100110512GBBits [38:15] must be zero
b1001111TBBits [39:15] must be zero
b1010002TBBits [40:15] must be zero
b1010014TBBits [41:15] must be zero
b1010108TBBits [42:15] must be zero
b10101116TBBits [43:15] must be zero
b10110032TBBits [44:15] must be zero
b10110164TBBits [45:15] must be zero
b101110128TBBits [46:15] must be zero
b101111256TBBits [47:15] must be zero
b110000512TBBits [48:15] must be zero
b1100011PBBits [49:15] must be zero
b1100102PBBits [50:15] must be zero
b1100114PBBits [51:15] must be zero
b1101008PBBits [52:15] must be zero
b11010116PBBits [53:15] must be zero
b11011032PBBits [54:15] must be zero
b11011164PBBits [55:15] must be zero
b111000128PBBits [56:15] must be zero
b111001256PBBits [57:15] must be zero
b111010512PBBits [58:15] must be zero
b1110111EBBits [59:15] must be zero
b1111002EBBits [60:15] must be zero
b1111014EBBits [61:15] must be zero
b1111108EBBits [62:15] must be zero
b11111116EBBits [63:15] must be zero

[a] The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 3.13 and Table 3.14.

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