4.2.3. Integration Test Output Register

The itop Register characteristics are:


Enables a processor to set the status of tzasc_int in integration test mode.

Usage constraints

Integration test logic must be enabled otherwise it ignores writes and reads return 0x0. See Integration Test Control Register for information about enabling the integration test logic.


Available in all configurations of the TZASC.


See the register summary in Table 4.1.

Figure 4.3 shows the itop Register bit assignments.

Figure 4.3. itop Register bit assignments

Table 4.4 shows the itop Register bit assignments.

Table 4.4. itop Register bit assignments

[31:1]-Read undefined. Write as zero.

Set or reset the value of tzasc_int port by writing 1 or 0 into itop_int bit. If you read, the written value can be read back.

0 = tzasc_int is LOW

1 = tzasc_int is HIGH.

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