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The periph_id_[4:0] Registers provide information about the configuration of the peripheral. Table 3.1 shows the address base offset, reset value, and access type for these registers.
Each register provides eight bits of data, but because some fields span across two adjacent periph_id registers, the following sections describe them:
Figure 3.16 shows the periph_id_[3:0] register group bit assignments.
Table 3.17 shows the periph_id_[3:0] register group bit assignments.
Table 3.17. periph_id_[3:0] Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:28] | RevAnd | Identifies the manufacturer revision number. |
| [27:24] | mod_number | Identifies data that is relevant to the ARM partner. |
| [23:20] | revision | Identifies the revision of the TZASC. |
| [19] | jedec_used | Identifies whether the TZASC uses the JEP106 manufacturer’s identity code. |
| [18:12] | JEP106[6:0] | Identifies the designer. This is set to b0111011, to indicate that ARM designed the peripheral. |
| [11:0] | part_number | Identifies the peripheral. The part number
for the TZASC is |
The following subsections describe the periph_id_[4:0] registers:
The periph_id_0 Register is hard-coded and the fields in the register control the reset value. Table 3.18 shows the register bit assignments.
Table 3.18. periph_id_0 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Reserved, read undefined |
| [7:0] | part_number_0 | These bits read back as 0x80 |
The periph_id_1 Register is hard-coded and the fields in the register control the reset value. Table 3.19 shows the register bit assignments.
Table 3.19. periph_id_1 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Reserved, read undefined. |
[7:4] | jep106_id_3_0 | JEP106 identity code [3:0]. See the JEP106, Standard Manufacturer’s Identification Code. These
bits read back as |
| [3:0] | part_number_1 | These bits read back as 0x3. |
The periph_id_2 Register is hard-coded and the fields in the register control the reset value. Table 3.20 shows the register bit assignments.
Table 3.20. periph_id_2 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Reserved, read undefined. |
[7:4] | revision | Identifies the revision of the TZASC.
For revision r0p0, this field is set to |
[3] | jedec_used | This indicates that the TZASC uses a
manufacturer’s identity code that was allocated by JEDEC according
to JEP106. This bit always reads back as |
[2:0] | jep106_id_6_4 | JEP106 identity code [6:4]. See the JEP106, Standard Manufacturer’s Identification Code. These bits read back as b011 because ARM is the designer of the peripheral. |
The periph_id_3 Register is hard-coded and the fields in the register control the reset value. Table 3.21 shows the register bit assignments.
Table 3.21. periph_id_3 Register bit assignments
Bit | Name | Description |
|---|---|---|
[31:8] | - | Undefined. |
[7:4] | RevAnd | The top-level RTL provides four AND gates that
are tied-off to provide an output value of 0x0. When
silicon is available, if metal fixes are necessary, the manufacturer
can modify the tie-offs to indicate that a revision of the silicon
has occurred. |
[3:0] | mod_number | You can update this field by modifying
the RTL of the TZASC. ARM sets this to |
The periph_id_4 Register is hard-coded and the fields in the register control the reset value. Figure 3.17 shows the periph_id_4 Register bit assignments.
Table 3.22 shows the register bit assignments.
Table 3.22. periph_id_4 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Undefined. |
[7:4] | 4KB_count | The number of 4KB address blocks you
require, to access the registers, expressed in powers of 2. These
bits read back as |
[3:0] | jep106_c_code | The JEP106 continuation code value represents
how many |