TrustZone® Address Space Controller (TZC-380) Technical Reference Manual

Revision: r0p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the TZASC
1.1.1. Features of the TZASC
1.2. Product revisions
2. Functional Description
2.1. Functional interfaces
2.1.1. AXI bus interfaces
2.1.2. APB slave interface
2.1.3. Miscellaneous signals
2.1.4. Clock and reset
2.2. Functional operation
2.2.1. Regions
2.2.2. Priority
2.2.3. Subregions
2.2.4. Subregion disable
2.2.5. Region security permissions
2.2.6. Denied AXI transactions
2.2.7. Speculative accesses
2.2.8. Preventing writes to registers and using secure_boot_lock
2.2.9. Using locked transaction sequences
2.2.10. Using exclusive accesses
2.3. Constraints of use
3. Programmers Model
3.1. About the programmers model
3.1.1. Register map
3.2. Register descriptions
3.2.1. Configuration Register
3.2.2. Action Register
3.2.3. Lockdown Range Register
3.2.4. Lockdown Select Register
3.2.5. Interrupt Status Register
3.2.6. Interrupt Clear Register
3.2.7. Fail Address Low Register
3.2.8. Fail Address High Register
3.2.9. Fail Control Register
3.2.10. Fail ID Register
3.2.11. Speculation Control Register
3.2.12. Security Inversion Enable Register
3.2.13. Region Setup Low <n> Register
3.2.14. Region Setup High <n> Register
3.2.15. Region Attributes <n> Register
3.2.16. Peripheral Identification Registers
3.2.17. Component Identification Registers
4. Programmers Model for Test
4.1. About the programmers model for test
4.2. Integration test registers
4.2.1. Integration Test Control Register
4.2.2. Integration Test Input Register
4.2.3. Integration Test Output Register
A. Signal Descriptions
A.1. Clock and reset signals
A.2. AXI signals
A.2.1. AXI slave interface signals
A.2.2. AXI master interface signals
A.3. APB signals
A.4. Miscellaneous signals
A.4.1. secure_boot_lock
A.4.2. Interrupt
B. Revisions

List of Tables

2.1. AXI slave interface attributes
2.2. AXI master interface attributes
2.3. Region security permissions when security inversion is disabled
2.4. Region security permissions when security inversion is enabled
2.5. Typical example of memory map along with the register programming
3.1. Register summary
3.2. configuration Register bit assignments
3.3. action Register bit assignments
3.4. lockdown_range Register bit assignments
3.5. lockdown_select Register bit assignments
3.6. int_status Register bit assignments
3.7. fail_address_low Register bit assignments
3.8. fail_address_high Register bit assignments
3.9. fail_control Register bit assignments
3.10. fail_id Register bit assignments
3.11. speculation_control Register bit assignments
3.12. security_inversion_en Register bit assignments
3.13. region_setup_low_<n> Register bit assignments
3.14. region_setup_high_<n> Register bit assignments
3.15. region_attributes_<n> Register bit assignments
3.16. Region size
3.17. periph_id_[3:0] Register bit assignments
3.18. periph_id_0 Register bit assignments
3.19. periph_id_1 Register bit assignments
3.20. periph_id_2 Register bit assignments
3.21. periph_id_3 Register bit assignments
3.22. periph_id_4 Register bit assignments
3.23. component_id Register bit assignments
3.24. component_id_0 Register bit assignments
3.25. component_id_1 Register bit assignments
3.26. component_id_2 Register bit assignments
3.27. component_id_3 Register bit assignments
4.1. Test register summary
4.2. itcrg Register bit assignments
4.3. itip Register bit assignments
4.4. itop Register bit assignments
A.1. Clock and reset signals
A.2. AXI-AW signals for the AXI slave interface
A.3. AXI-W signals for the AXI slave interface
A.4. AXI-B signals for the AXI slave interface
A.5. AXI-AR signals for the AXI slave interface
A.6. AXI-R signals for the AXI slave interface
A.7. AXI-AW signals for the AXI master interface
A.8. AXI-W signals for the AXI master interface
A.9. AXI-B signals for the AXI master interface
A.10. AXI-AR signals for the AXI master interface
A.11. AXI-R signals for the AXI master interface
A.12. APB slave interface signals
A.13. secure_boot_lock signal
A.14. tzasc_int signal
B.1. Differences between issue A and issue B

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A10 September 2008First release for r0p0
Revision B19 March 2010Second release for r0p0
Copyright © 2008, 2010 ARM Limited. All rights reserved.ARM DDI 0431B